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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: J0Uz83wK47vqyBBJddU8iMB72nu+fWyErPm6YjFqNXs6c4ZnGbDeodGp5HD5+MCKWXC2tLHgVDQNTg1tkdv554zx9z7uruc9bws1/FzAZkim782xgUmIU+Xyf7VryRJmqw9gOATbz28x1dBNY7wq27/yXqSehESGuJtvQQs6z5BMB6qYPrez1uHJKn1AfHOFoBEbpD7eh0cUmoaD6brlpFoLzD2pebJuDpKmVMXOEPpvp0nIsja1zfgtL+0L2AKh47YJK4Nr/5bJlPY2Xh+KvytRmCvxtRpnMhZGYuHIQ30rUdC7t4g036Tk6JmW7b5Rlurvoid+DyzBiQnDWmarJhkMROYZfLM0xM9hScmvdvBbvzNYwk1yxZGfhTcXAlFaQEeOfYkb19tOBaCOmtWsV6CVl6QAldWNBf0Tbq6HFuDs0JueVHgnO3m+KpJtHhjL Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b19f7ace-f013-416f-5e97-08d75b541e39 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2019 03:08:34.0350 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pKHHI1b8+d5j+8eEnI8oFH+rWBL4R+mx7C9Jf31n0q/Tw+jlw44stTT+8zVUdsEKPXHw97OHv/M/A9IvANTUVw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5667 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent. According to the current imx_clk_sccg_pll design, it uses both bypass1/2, however set bypass2 as 1 is not correct, because it will make sys[x]_pll_out use wrong parent and might access wrong registers. So correct bypass2 to 0 and fix sys3_pll_out_sels. Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") Signed-off-by: Peng Fan --- V2: Rebased on Shawn's clk/imx tree to avoid conflicts drivers/clk/imx/clk-imx8mq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 4a5dbc4366a5..5f10a606d836 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -34,7 +34,7 @@ static const char * const audio_pll1_bypass_sels[] =3D {"= audio_pll1", "audio_pll1_ static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", "vid= eo_pll1_ref_sel", }; =20 -static const char * const sys3_pll_out_sels[] =3D {"sys3_pll1_ref_sel", "s= ys2_pll1_ref_sel", }; +static const char * const sys3_pll_out_sels[] =3D {"sys3_pll1_ref_sel", }; static const char * const dram_pll_out_sels[] =3D {"dram_pll1_ref_sel", }; static const char * const video2_pll_out_sels[] =3D {"video2_pll1_ref_sel"= , }; =20 @@ -342,7 +342,7 @@ static int imx8mq_clocks_probe(struct platform_device *= pdev) =20 clks[IMX8MQ_SYS1_PLL_OUT] =3D imx_clk_fixed("sys1_pll_out", 800000000); clks[IMX8MQ_SYS2_PLL_OUT] =3D imx_clk_fixed("sys2_pll_out", 1000000000); - clks[IMX8MQ_SYS3_PLL_OUT] =3D imx_clk_sccg_pll("sys3_pll_out", sys3_pll_o= ut_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITIC= AL); + clks[IMX8MQ_SYS3_PLL_OUT] =3D imx_clk_sccg_pll("sys3_pll_out", sys3_pll_o= ut_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITIC= AL); clks[IMX8MQ_DRAM_PLL_OUT] =3D imx_clk_sccg_pll("dram_pll_out", dram_pll_o= ut_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITIC= AL); clks[IMX8MQ_VIDEO2_PLL_OUT] =3D imx_clk_sccg_pll("video2_pll_out", video2= _pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0); =20 --=20 2.16.4