From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2499CC2D0BF for ; Tue, 17 Dec 2019 20:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ACBDA24688 for ; Tue, 17 Dec 2019 20:04:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="nmmbHmYh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728132AbfLQUEY (ORCPT ); Tue, 17 Dec 2019 15:04:24 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1836 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728092AbfLQUEY (ORCPT ); Tue, 17 Dec 2019 15:04:24 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 17 Dec 2019 12:04:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 17 Dec 2019 12:04:23 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 17 Dec 2019 12:04:23 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 17 Dec 2019 20:04:22 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 17 Dec 2019 20:04:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.174.101]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 17 Dec 2019 12:04:22 -0800 From: Sowjanya Komatineni To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v4 16/19] arm64: tegra: Add clock-cells property to Tegra PMC node Date: Tue, 17 Dec 2019 12:04:03 -0800 Message-ID: <1576613046-17159-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576613046-17159-1-git-send-email-skomatineni@nvidia.com> References: <1576613046-17159-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576613053; bh=OwD06PBgErowUtwVp1OBcA4PCkJ/Hokw0VEfm2MxLTI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=nmmbHmYhf5z+4Rsfe1EkEXGjwfGkDaGFVJMAzQHr9M4Gm5cTPX7XaG1Zux7J4ge7W 6u3uIP9qSO8G9Zjatbzl4HEp3m7ml4NSuyP8IRBJ8Io+IlmQEtGElhUtO2Je2pw1ax nNw6atkVG2G/C8OxiUZiRd1B15aHGTvG4Bx/tqPBoJ9J6T9uuhIL68otDPlJBI5OOm Kz49n/HVwXuVl7+4ysPpHcJ+blT2WjgmlFlS8oQIIWej9kfNoCyBA3UFheXr6pesgq Aa5NwUxzkK3Y76PzotwMDfkf6RFMK3uA297nrMeam1hWEcusFYcvvL2b4lGb/y5roz ayMCH/CWnMm7g== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3, and a blink clock as a part of PMC. These clocks are moved from clock driver to pmc driver with pmc as a clock provider. Clock ids for these clocks are defined in pmc dt-bindings. This patch updated device tree to include pmc dt-binding and adds #clock-cells property with one clock specifier to pmc node. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 631a7f77c386..5bdb4a6a6b90 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra132", "nvidia,tegra124"; @@ -577,11 +578,12 @@ clock-names = "rtc"; }; - pmc@7000e400 { + pmc: pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 48c63256ba7f..0d0432d3b37a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra210"; @@ -780,6 +781,7 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; #interrupt-cells = <2>; interrupt-controller; -- 2.7.4