From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8384FC43603 for ; Tue, 17 Dec 2019 20:05:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5611620716 for ; Tue, 17 Dec 2019 20:05:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="c1TXials" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728428AbfLQUFf (ORCPT ); Tue, 17 Dec 2019 15:05:35 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2767 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727036AbfLQUEP (ORCPT ); Tue, 17 Dec 2019 15:04:15 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 17 Dec 2019 12:03:46 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 17 Dec 2019 12:04:14 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 17 Dec 2019 12:04:14 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 17 Dec 2019 20:04:14 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 17 Dec 2019 20:04:14 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.174.101]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 17 Dec 2019 12:04:14 -0800 From: Sowjanya Komatineni To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Date: Tue, 17 Dec 2019 12:03:52 -0800 Message-ID: <1576613046-17159-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576613046-17159-1-git-send-email-skomatineni@nvidia.com> References: <1576613046-17159-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576613026; bh=SJs0uOhQMCX7QeE3qqpJsedMWOcbK6k/CG0iYVIjl1Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=c1TXialsDi8iCNcGwAaeO5aEOlk0D0fTEiyOamVV0KPJXbhMPA4q1dj+Ya3bmRBne PmDYOqGpis9tIefyds/YnqHRXyDfdUT8GeZBrhmMyewoJnYFwyWHrKZ5rujOqUNDfx 6B/fFCSswPoWWk2EkFfRrTKjlVPQbPJLk4+pc+r71tZcojTQuZqb7uKD2GmHsUhQTq C1mG+QYH8oxFMdKdR/0aMFeiDPWNFhXtFahJ26vFTpS5OklONJFtVN/rSGI+B0dJsH ADOKIHO4lTKnoFvAlsf2dz5v2Ox0alYwX4n76e7FfyAaKhmFcHgHk5trRTJQfo1JXf thIf5oyWTELyA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3. This patch documents PMC clock bindings and adds a header defining Tegra PMC clock ids. Signed-off-by: Sowjanya Komatineni --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 37 +++++++++++++++++++++- include/dt-bindings/soc/tegra-pmc.h | 15 +++++++++ 2 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/soc/tegra-pmc.h diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index cb12f33a247f..80cdcad4ab8c 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -21,6 +21,10 @@ Required properties: - clock-names : Must include the following entries: "pclk" (The Tegra clock of that name), "clk32k_in" (The 32KHz clock input to Tegra). +- #clock-cells : Should be 1 for Tegra30 and higher. + In clock consumers, this cell represents the PMC clock ID. + The assignments may be found in header file + . Optional properties: - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. @@ -80,11 +84,12 @@ Optional nodes: Example: / SoC dts including file -pmc@7000f400 { +pmc: pmc@7000f400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car 110>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -171,6 +176,7 @@ Example: reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; powergates { pd_audio: aud { @@ -260,6 +266,7 @@ Pad configuration state example: reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; ... @@ -298,3 +305,31 @@ Pinctrl client example: pinctrl-1 = <&hdmi_on>; pinctrl-names = "hdmi-on", "hdmi-off"; }; + +== Clock Control == + +Tegra PMC has 3 clocks clk_1, clk_2 and clk_3. Each of these clocks has +source selection and enable/disable gate. +Parent/source for these clocks can be either of osc, osc_div2, osc_div4, +or extern clock from Tegra CAR module. + +Clock configuration example: + pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + }; + +Clock consumer example: + i2c@7000c500 { + cam_sensor { + ... + clocks = <&pmc TEGRA_PMC_CLK_OUT_3>; + clock-names = "mclk"; + assigned-clocks = <&pmc TEGRA_PMC_CLK_OUT_3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_EXTERN3>; + ... + }; + }; diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h new file mode 100644 index 000000000000..f7c866404456 --- /dev/null +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +#define _DT_BINDINGS_SOC_TEGRA_PMC_H + +#define TEGRA_PMC_CLK_OUT_1 0 +#define TEGRA_PMC_CLK_OUT_2 1 +#define TEGRA_PMC_CLK_OUT_3 2 + +#define TEGRA_PMC_CLK_MAX 3 + +#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ -- 2.7.4