[PATCH 00/12] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers

[Weiyi Lu <weiyi.lu@mediatek.com>]

This series is based on v5.9-rc1 and
[v4,09/34] clk: mediatek: Fix asymmetrical PLL enable and disable control[1]
in Mediatek MT8192 clock support series

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1603370247-30437-10-git-send-email-weiyi.lu@mediatek.com/

Weiyi Lu (12):
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516
  clk: mediatek: limit en_mask to a pure div_en_mask

 drivers/clk/mediatek/clk-mt2701.c | 26 +++++++++++++-------------
 drivers/clk/mediatek/clk-mt2712.c | 30 +++++++++++++++---------------
 drivers/clk/mediatek/clk-mt6765.c | 20 ++++++++++----------
 drivers/clk/mediatek/clk-mt6779.c | 24 ++++++++++++------------
 drivers/clk/mediatek/clk-mt6797.c | 20 ++++++++++----------
 drivers/clk/mediatek/clk-mt7622.c | 18 +++++++++---------
 drivers/clk/mediatek/clk-mt7629.c | 12 ++++++------
 drivers/clk/mediatek/clk-mt8135.c | 20 ++++++++++----------
 drivers/clk/mediatek/clk-mt8173.c | 28 ++++++++++++++--------------
 drivers/clk/mediatek/clk-mt8183.c | 22 +++++++++++-----------
 drivers/clk/mediatek/clk-mt8516.c | 12 ++++++------
 drivers/clk/mediatek/clk-pll.c    | 12 ++++--------
 12 files changed, 120 insertions(+), 124 deletions(-)