[PATCH v2 7/7] arm64: dts: mt8192: Add APU power domain node

Flora Fu
2021-04-15T05:53:04Z

Add APU power domain node to MT8192.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
---
Note:
This patch depends on MT8192 clock[1] and PMIC[2] patches which haven't yet been accepted.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.chen@mediatek.com/
[2] https://patchwork.kernel.org/project/linux-mediatek/patch/1617188527-3392-9-git-send-email-hsin-hsiung.wang@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 ++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 28 +++++++++++++++++++++
2 files changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 1769f3a9b510..688c97c46d44 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -65,3 +65,10 @@
&mt6359_vrf12_ldo_reg {
regulator-always-on;
};
+
+&apuspm {
+ vsram-supply = <&mt6359_vsram_md_ldo_reg>;
+ apu_top: power-domain@0 {
+ domain-supply = <&mt6359_vproc1_buck_reg>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 561025d2ebab..90436757386e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1033,6 +1033,34 @@
#clock-cells = <1>;
};

+ apuspm: power-domain@190f0000 {
+ compatible = "mediatek,mt8192-apu-pm", "syscon";
+ reg = <0 0x190f0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ mediatek,scpsys = <&scpsys>;
+ mediatek,apu-conn = <&apu_conn>;
+ mediatek,apu-vcore = <&apu_vcore>;
+
+ apu_top: power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+ clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+ assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+ };
+ };
+
larb13: larb@1a001000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
--
2.18.0