Linux clock framework development
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From: Bjorn Andersson <andersson@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: stable@vger.kernel.org, Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Dmitry Baryshkov <lumag@kernel.org>
Subject: Re: [PATCH v6] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks
Date: Wed, 11 Jun 2025 23:00:40 -0500	[thread overview]
Message-ID: <174970084199.547582.700390478777102209.b4-ty@kernel.org> (raw)
In-Reply-To: <20250520090741.45820-2-krzysztof.kozlowski@linaro.org>


On Tue, 20 May 2025 11:07:42 +0200, Krzysztof Kozlowski wrote:
> On SM8750 the setting rate of pixel and byte clocks, while the parent
> DSI PHY PLL, fails with:
> 
>   disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
> 
> DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in
> CMN_CTRL_0 asserted.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks
      commit: 0acf9e65a47d1e489c8b24c45a64436e30bcccf4

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

      parent reply	other threads:[~2025-06-12  4:01 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-20  9:07 [PATCH v6] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks Krzysztof Kozlowski
2025-05-20 21:27 ` Dmitry Baryshkov
2025-05-20 21:52 ` Abhinav Kumar
2025-06-12  4:00 ` Bjorn Andersson [this message]

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