Re: [PATCH v5] clk: socfpga: agilex: add support for the Intel Agilex5

Stephen Boyd
2025-09-21T17:59:52Z

Quoting Matthew Gerlach (2025-07-02 09:04:17)
> On 6/30/25 6:05 PM, Stephen Boyd wrote:
> > Quoting Matthew Gerlach (2025-05-13 16:48:37)
> > > @@ -334,6 +336,375 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
> > > 10, 0, 0, 0, 0, 0, 4},
> > > };
> > >
> > > +static const struct clk_parent_data agilex5_pll_mux[] = {
> > > + { .name = "osc1", },
> > > + { .name = "cb-intosc-hs-div2-clk", },
> > > + { .name = "f2s-free-clk", },
> >
> > Please don't use clk_parent_data with only .name set with dot
> > initializers. This is actually { .index = 0, .name = "..." } which means
> > the core is looking at the DT node for the first index of the 'clocks'
> If the core should be looking for the first index of the 'clocks'
> property, is it better to explicitly to state ".index = 0" or just have
> the name?

Be explicit with '.index = 0' and don't have a '.name' member.