[PATCH 15/19] clk: eyeq: add a type for the PLL

Benoît Monin
2025-09-03T12:48:07Z

Add a type field to the eqc_pll structure and parse the registers of
the PLL depending on its type. This makes room for adding new PLL types
found in the eyeQ7H OLB.

Each PLL type now comes with its own registers parsing function that is
called based on the type.

For now, only the FRACG type is implemented.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 104 +++++++++++++++++++++++++++----------------------
1 file changed, 57 insertions(+), 47 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 0379fe7593453e72dd8983c743561caa385a3fbd..07a205fefd93eed8f9c2c6b88fbf5b8b6a39a92c 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -70,10 +70,15 @@
#define FRACG_PCSR1_DOWN_SPREAD BIT(11)
#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12)

+enum eqc_pll_type {
+ EQC_PLL_FRACG,
+};
+
struct eqc_pll {
- unsigned int index;
- const char *name;
- unsigned int reg;
+ unsigned int index;
+ const char *name;
+ unsigned int reg;
+ enum eqc_pll_type type;
};

/*
@@ -162,11 +167,17 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div)
*div >>= shift;
}

-static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
- unsigned long *div, unsigned long *acc)
+static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
+ unsigned long *div, unsigned long *acc)
{
+ u64 val;
+ u32 r0, r1;
u32 spread;

+ val = readq(base);
+ r0 = val;
+ r1 = val >> 32;
+
if (r0 & FRACG_PCSR0_BYPASS) {
*mult = 1;
*div = 1;
@@ -225,6 +236,16 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
return 0;
}

+static int eqc_parse_one_pll(void __iomem *base, enum eqc_pll_type type, unsigned long *mult,
+ unsigned long *div, unsigned long *acc)
+{
+ switch (type) {
+ case EQC_PLL_FRACG:
+ return eqc_pll_parse_fracg(base, mult, div, acc);
+ }
+ return -EINVAL;
+}
+
static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data *data,
void __iomem *base, struct clk_hw_onecell_data *cells)
{
@@ -232,18 +253,12 @@ static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data
const struct eqc_pll *pll;
struct clk_hw *hw;
unsigned int i;
- u32 r0, r1;
- u64 val;
int ret;

for (i = 0; i < data->pll_count; i++) {
pll = &data->plls[i];

- val = readq(base + pll->reg);
- r0 = val;
- r1 = val >> 32;
-
- ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc);
+ ret = eqc_parse_one_pll(base + pll->reg, pll->type, &mult, &div, &acc);
if (ret) {
dev_warn(dev, "failed parsing state of %s\n", pll->name);
cells->hws[pll->index] = ERR_PTR(ret);
@@ -422,19 +437,19 @@ static int eqc_probe(struct platform_device *pdev)

/* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
static const struct eqc_pll eqc_eyeq5_early_plls[] = {
- { .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg = 0x02C },
- { .index = EQ5C_PLL_PER, .name = "pll-per", .reg = 0x05C },
+ { .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg = 0x02C, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_PER, .name = "pll-per", .reg = 0x05C, .type = EQC_PLL_FRACG },
};

static const struct eqc_pll eqc_eyeq5_plls[] = {
- { .index = EQ5C_PLL_VMP, .name = "pll-vmp", .reg = 0x034 },
- { .index = EQ5C_PLL_PMA, .name = "pll-pma", .reg = 0x03C },
- { .index = EQ5C_PLL_VDI, .name = "pll-vdi", .reg = 0x044 },
- { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x04C },
- { .index = EQ5C_PLL_PCI, .name = "pll-pci", .reg = 0x054 },
- { .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x064 },
- { .index = EQ5C_PLL_MPC, .name = "pll-mpc", .reg = 0x06C },
- { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x074 },
+ { .index = EQ5C_PLL_VMP, .name = "pll-vmp", .reg = 0x034, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_PMA, .name = "pll-pma", .reg = 0x03C, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_VDI, .name = "pll-vdi", .reg = 0x044, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x04C, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_PCI, .name = "pll-pci", .reg = 0x054, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x064, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_MPC, .name = "pll-mpc", .reg = 0x06C, .type = EQC_PLL_FRACG },
+ { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x074, .type = EQC_PLL_FRACG },
};

enum {
@@ -562,10 +577,11 @@ static const struct eqc_match_data eqc_eyeq5_match_data = {
};

static const struct eqc_pll eqc_eyeq6l_plls[] = {
- { .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg = 0x02C },
- { .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg = 0x034 }, /* also acc */
- { .index = EQ6LC_PLL_PER, .name = "pll-per", .reg = 0x03C },
- { .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg = 0x044 },
+ { .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg = 0x02C, .type = EQC_PLL_FRACG },
+ /* pll-cpu also for acc */
+ { .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg = 0x034, .type = EQC_PLL_FRACG },
+ { .index = EQ6LC_PLL_PER, .name = "pll-per", .reg = 0x03C, .type = EQC_PLL_FRACG },
+ { .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg = 0x044, .type = EQC_PLL_FRACG },
};

static const struct eqc_match_data eqc_eyeq6l_match_data = {
@@ -580,7 +596,7 @@ static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
};

static const struct eqc_pll eqc_eyeq6h_east_plls[] = {
- { .index = 0, .name = "pll-east", .reg = 0x074 },
+ { .index = 0, .name = "pll-east", .reg = 0x074, .type = EQC_PLL_FRACG },
};

static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
@@ -591,10 +607,10 @@ static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
};

static const struct eqc_pll eqc_eyeq6h_south_plls[] = {
- { .index = EQ6HC_SOUTH_PLL_VDI, .name = "pll-vdi", .reg = 0x000 },
- { .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg = 0x008 },
- { .index = EQ6HC_SOUTH_PLL_PER, .name = "pll-per", .reg = 0x010 },
- { .index = EQ6HC_SOUTH_PLL_ISP, .name = "pll-isp", .reg = 0x018 },
+ { .index = EQ6HC_SOUTH_PLL_VDI, .name = "pll-vdi", .reg = 0x000, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg = 0x008, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_SOUTH_PLL_PER, .name = "pll-per", .reg = 0x010, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_SOUTH_PLL_ISP, .name = "pll-isp", .reg = 0x018, .type = EQC_PLL_FRACG },
};

static const struct eqc_div eqc_eyeq6h_south_divs[] = {
@@ -641,7 +657,7 @@ static const struct eqc_match_data eqc_eyeq6h_south_match_data = {
};

static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] = {
- { .index = 0, .name = "pll-ddr0", .reg = 0x074 },
+ { .index = 0, .name = "pll-ddr0", .reg = 0x074, .type = EQC_PLL_FRACG },
};

static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
@@ -650,7 +666,7 @@ static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
};

static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] = {
- { .index = 0, .name = "pll-ddr1", .reg = 0x074 },
+ { .index = 0, .name = "pll-ddr1", .reg = 0x074, .type = EQC_PLL_FRACG },
};

static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
@@ -659,11 +675,11 @@ static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
};

static const struct eqc_pll eqc_eyeq6h_acc_plls[] = {
- { .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg = 0x040 },
- { .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg = 0x050 },
- { .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg = 0x05C },
- { .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg = 0x068 },
- { .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg = 0x070 },
+ { .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg = 0x040, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg = 0x050, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg = 0x05C, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg = 0x068, .type = EQC_PLL_FRACG },
+ { .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg = 0x070, .type = EQC_PLL_FRACG },
};

static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
@@ -697,7 +713,7 @@ builtin_platform_driver(eqc_driver);

/* Required early for GIC timer. */
static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = {
- { .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg = 0x02C },
+ { .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg = 0x02C, .type = EQC_PLL_FRACG },
};

static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = {
@@ -714,7 +730,7 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i

/* Required early for UART. */
static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {
- { .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg = 0x074 },
+ { .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg = 0x074, .type = EQC_PLL_FRACG },
};

static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {
@@ -769,14 +785,8 @@ static void __init eqc_early_init(struct device_node *np,
const struct eqc_pll *pll = &early_data->early_plls[i];
unsigned long mult, div, acc;
struct clk_hw *hw;
- u32 r0, r1;
- u64 val;

- val = readq(base + pll->reg);
- r0 = val;
- r1 = val >> 32;
-
- ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc);
+ ret = eqc_parse_one_pll(base + pll->reg, pll->type, &mult, &div, &acc);
if (ret) {
pr_err("failed parsing state of %s\n", pll->name);
goto err;

--
2.51.0