[PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ

Benoît Monin
2025-09-03T12:47:46Z

Define the indexes of the reset controllers present in 11 of the OLB
found in Mobileye eyeQ7H SoC. The define names start with EQ7HR, which
is the abbreviation of EyeQ7H Reset.

For the OLBs with multiple reset domains, the domain number is in the
define name (DOMx) and should also be passed in the device tree:

resets = <&olb_south 0 EQ7HR_SOUTH_DOM0_PCI_CTL>;

For the OLBs with a single reset domain, only the reset index is needed:

resets = <&olb_periph_west EQ7HR_PERIPH_UART>;

Some reset indexes are common between two OLB:
* EQ7HR_PERIPH defines the reset indexes of OLB periph_east and
periph_west.
* EQ7HR_DDR defines the reset indexes of OLB ddr0 and ddr1.
* EQ7HR_ACC defines the reset indexes of OLB acc0 and acc1.
* EQ7HR_XNN defines the reset indexes of OLB xnn0 and xnn1.

Signed-off-by: Sari Khoury <sari.khoury@mobileye.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
MAINTAINERS | 1 +
include/dt-bindings/reset/mobileye,eyeq-reset.h | 75 +++++++++++++++++++++++++
2 files changed, 76 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c56f17e4c585fe3e719fbae18b70a0c132c5da48..6e6bf23e988ad9b8d77268f680ea4dee0489684f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17113,6 +17113,7 @@ F: drivers/clk/clk-eyeq.c
F: drivers/pinctrl/pinctrl-eyeq5.c
F: drivers/reset/reset-eyeq.c
F: include/dt-bindings/clock/mobileye,eyeq-clk.h
+F: include/dt-bindings/reset/mobileye,eyeq-reset.h

MODULE SUPPORT
M: Luis Chamberlain <mcgrof@kernel.org>
diff --git a/include/dt-bindings/reset/mobileye,eyeq-reset.h b/include/dt-bindings/reset/mobileye,eyeq-reset.h
new file mode 100644
index 0000000000000000000000000000000000000000..70d3b7140f8d2599186c7ddff32b8131e90c644e
--- /dev/null
+++ b/include/dt-bindings/reset/mobileye,eyeq-reset.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_MOBILEYE_EYEQ_RESET_H
+#define _DT_BINDINGS_MOBILEYE_EYEQ_RESET_H
+
+#define EQ7HR_SOUTH_DOM0_PCI_PHY 0
+#define EQ7HR_SOUTH_DOM0_PCI_CTL 1
+#define EQ7HR_SOUTH_DOM0_S_NOC 2
+#define EQ7HR_SOUTH_DOM0_GBE_PHY 3
+#define EQ7HR_SOUTH_DOM0_GBE_CTL 4
+
+#define EQ7HR_SOUTH_DOM1_XSPI 0
+#define EQ7HR_SOUTH_DOM1_UFS 1
+#define EQ7HR_SOUTH_DOM1_S_VDIO 2
+
+#define EQ7HR_EAST_ISP 0
+#define EQ7HR_EAST_VEU 1
+#define EQ7HR_EAST_LBIST 2
+
+#define EQ7HR_WEST_GPU 0
+#define EQ7HR_WEST_CAU 1
+#define EQ7HR_WEST_LBIST 2
+#define EQ7HR_WEST_GPU_LBIST 3
+
+#define EQ7HR_PERIPH_GPIO 0
+#define EQ7HR_PERIPH_EXT 1
+#define EQ7HR_PERIPH_UART 2
+#define EQ7HR_PERIPH_SPI 3
+#define EQ7HR_PERIPH_I2C0 4
+#define EQ7HR_PERIPH_I2C1 5
+#define EQ7HR_PERIPH_I2C2 6
+#define EQ7HR_PERIPH_I2S 7
+
+#define EQ7HR_DDR_APB 0
+#define EQ7HR_DDR_DMI 1
+#define EQ7HR_DDR_DFI 2
+#define EQ7HR_DDR_PHY_SMS 3
+#define EQ7HR_DDR_CTL_SMS 4
+
+#define EQ7HR_ACC_DOM0_VMP0 0
+#define EQ7HR_ACC_DOM0_VMP1 1
+#define EQ7HR_ACC_DOM0_VMP2 2
+#define EQ7HR_ACC_DOM0_VMP3 3
+#define EQ7HR_ACC_DOM0_MPC0 4
+#define EQ7HR_ACC_DOM0_MPC1 5
+#define EQ7HR_ACC_DOM0_PMA0 6
+#define EQ7HR_ACC_DOM0_PMA1 7
+
+#define EQ7HR_ACC_DOM1_NCORE0 0
+#define EQ7HR_ACC_DOM1_NCORE1 1
+#define EQ7HR_ACC_DOM1_NCORE0_M 2
+#define EQ7HR_ACC_DOM1_NCORE1_M 3
+#define EQ7HR_ACC_DOM1_NCORE_NOC 4
+#define EQ7HR_ACC_DOM1_VMP_NOC 5
+#define EQ7HR_ACC_DOM1_MPC_NOC 6
+#define EQ7HR_ACC_DOM1_PMA_NOC 7
+
+#define EQ7HR_XNN_DOM0_XNN0 0
+#define EQ7HR_XNN_DOM0_XNN1 1
+#define EQ7HR_XNN_DOM0_XNN2 2
+
+#define EQ7HR_XNN_DOM1_XNN0 0
+#define EQ7HR_XNN_DOM1_XNN1 1
+#define EQ7HR_XNN_DOM1_XNN2 2
+#define EQ7HR_XNN_DOM1_XNN3 3
+#define EQ7HR_XNN_DOM1_NCORE 4
+#define EQ7HR_XNN_DOM1_I2_0 5
+#define EQ7HR_XNN_DOM1_I2_1 6
+#define EQ7HR_XNN_DOM1_SMS_0 7
+#define EQ7HR_XNN_DOM1_SMS_1 8
+
+#endif

--
2.51.0