[PATCH 13/19] clk: eyeq: prefix the PLL registers with the PLL type

Benoît Monin
2025-09-03T12:48:02Z

Rename the PLL registers to make room for other PLL types that are
present in the eyeQ7H.

We only prefix the register with the PLL type (FRACG), no other change.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
drivers/clk/clk-eyeq.c | 50 +++++++++++++++++++++++++-------------------------
1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index a0581016100c7367efb373a3fb3b7c6d51b49912..63093a3099261e6798a6752651d25efa1b3e7592 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -47,28 +47,28 @@
#include <dt-bindings/clock/mobileye,eyeq-clk.h>

/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
-#define PCSR0_DAC_EN BIT(0)
+#define FRACG_PCSR0_DAC_EN BIT(0)
/* Fractional or integer mode */
-#define PCSR0_DSM_EN BIT(1)
-#define PCSR0_PLL_EN BIT(2)
+#define FRACG_PCSR0_DSM_EN BIT(1)
+#define FRACG_PCSR0_PLL_EN BIT(2)
/* All clocks output held at 0 */
-#define PCSR0_FOUTPOSTDIV_EN BIT(3)
-#define PCSR0_POST_DIV1 GENMASK(6, 4)
-#define PCSR0_POST_DIV2 GENMASK(9, 7)
-#define PCSR0_REF_DIV GENMASK(15, 10)
-#define PCSR0_INTIN GENMASK(27, 16)
-#define PCSR0_BYPASS BIT(28)
+#define FRACG_PCSR0_FOUTPOSTDIV_EN BIT(3)
+#define FRACG_PCSR0_POST_DIV1 GENMASK(6, 4)
+#define FRACG_PCSR0_POST_DIV2 GENMASK(9, 7)
+#define FRACG_PCSR0_REF_DIV GENMASK(15, 10)
+#define FRACG_PCSR0_INTIN GENMASK(27, 16)
+#define FRACG_PCSR0_BYPASS BIT(28)
/* Bits 30..29 are reserved */
-#define PCSR0_PLL_LOCKED BIT(31)
+#define FRACG_PCSR0_PLL_LOCKED BIT(31)

-#define PCSR1_RESET BIT(0)
-#define PCSR1_SSGC_DIV GENMASK(4, 1)
+#define FRACG_PCSR1_RESET BIT(0)
+#define FRACG_PCSR1_SSGC_DIV GENMASK(4, 1)
/* Spread amplitude (% = 0.1 * SPREAD[4:0]) */
-#define PCSR1_SPREAD GENMASK(9, 5)
-#define PCSR1_DIS_SSCG BIT(10)
+#define FRACG_PCSR1_SPREAD GENMASK(9, 5)
+#define FRACG_PCSR1_DIS_SSCG BIT(10)
/* Down-spread or center-spread */
-#define PCSR1_DOWN_SPREAD BIT(11)
-#define PCSR1_FRAC_IN GENMASK(31, 12)
+#define FRACG_PCSR1_DOWN_SPREAD BIT(11)
+#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12)

struct eqc_pll {
unsigned int index;
@@ -167,29 +167,29 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
{
u32 spread;

- if (r0 & PCSR0_BYPASS) {
+ if (r0 & FRACG_PCSR0_BYPASS) {
*mult = 1;
*div = 1;
*acc = 0;
return 0;
}

- if (!(r0 & PCSR0_PLL_LOCKED))
+ if (!(r0 & FRACG_PCSR0_PLL_LOCKED))
return -EINVAL;

- *mult = FIELD_GET(PCSR0_INTIN, r0);
- *div = FIELD_GET(PCSR0_REF_DIV, r0);
+ *mult = FIELD_GET(FRACG_PCSR0_INTIN, r0);
+ *div = FIELD_GET(FRACG_PCSR0_REF_DIV, r0);

/* Fractional mode, in 2^20 (0x100000) parts. */
- if (r0 & PCSR0_DSM_EN) {
+ if (r0 & FRACG_PCSR0_DSM_EN) {
*div *= (1ULL << 20);
- *mult = *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1);
+ *mult = *mult * (1ULL << 20) + FIELD_GET(FRACG_PCSR1_FRAC_IN, r1);
}

if (!*mult || !*div)
return -EINVAL;

- if (r1 & (PCSR1_RESET | PCSR1_DIS_SSCG)) {
+ if (r1 & (FRACG_PCSR1_RESET | FRACG_PCSR1_DIS_SSCG)) {
*acc = 0;
return 0;
}
@@ -204,10 +204,10 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
* with acc in parts per billion and,
* spread in parts per thousand.
*/
- spread = FIELD_GET(PCSR1_SPREAD, r1);
+ spread = FIELD_GET(FRACG_PCSR1_SPREAD, r1);
*acc = spread * 500000;

- if (r1 & PCSR1_DOWN_SPREAD) {
+ if (r1 & FRACG_PCSR1_DOWN_SPREAD) {
/*
* Downspreading: the central frequency is half a
* spread lower.

--
2.51.0