From: "Heiko Stübner" <heiko@sntech.de>
To: dri-devel@lists.freedesktop.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Yakir Yang <kuankuan.y@gmail.com>,
Jeffy Chen <jeffy.chen@rock-chips.com>,
Jonas Karlman <jonas@kwiboo.se>
Cc: linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Jonas Karlman <jonas@kwiboo.se>,
linux-clk@vger.kernel.org
Subject: Re: [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
Date: Mon, 17 Jun 2024 22:30:25 +0200 [thread overview]
Message-ID: <19757196.sIn9rWBj0N@diego> (raw)
In-Reply-To: <20240615170417.3134517-3-jonas@kwiboo.se>
Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman:
> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
> parented by the hdmiphy clk and it is expected that the DCLK_VOP and
> hdmiphy clk rate are kept in sync.
>
> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
> on RK3328, to make full use of all possible supported display modes.
>
> Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
> Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
did your mailer have a hickup? Somehow I got patch2 (only this one)
2 times
next prev parent reply other threads:[~2024-06-17 20:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240615170417.3134517-1-jonas@kwiboo.se>
2024-06-15 17:03 ` [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 Jonas Karlman
2024-06-17 20:30 ` Heiko Stübner [this message]
2024-06-17 20:50 ` Jonas Karlman
2024-06-17 20:56 ` Dragan Simic
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