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charset="utf-8" Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <9914729c-8e69-4ad5-a530-161f5430b71d@nvidia.com> References: <20240906113905.641336-1-quic_skakitap@quicinc.com> <9914729c-8e69-4ad5-a530-161f5430b71d@nvidia.com> Subject: Re: [PATCH V3] clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val() From: Stephen Boyd Cc: Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ajit Pandey , Taniya Das , Imran Shaik , Jagadeesh Kona , Dan Carpenter , Vladimir Zapolskiy , kernel test robot , linux-tegra@vger.kernel.org To: Bjorn Andersson , Jon Hunter , Michael Turquette , Satya Priya Kakitapalli Date: Mon, 09 Sep 2024 14:08:07 -0700 User-Agent: alot/0.10 Quoting Jon Hunter (2024-09-09 03:57:09) >=20 > On 06/09/2024 15:14, Jon Hunter wrote: > >=20 > > On 06/09/2024 12:39, Satya Priya Kakitapalli wrote: > >> In zonda_pll_adjust_l_val() replace the divide operator with comparison > >> operator to fix below build error and smatch warning. > >> > >> drivers/clk/qcom/clk-alpha-pll.o: In function `clk_zonda_pll_set_rate': > >> clk-alpha-pll.c:(.text+0x45dc): undefined reference to `__aeabi_uldivm= od' > >> > >> smatch warnings: > >> drivers/clk/qcom/clk-alpha-pll.c:2129 zonda_pll_adjust_l_val() warn:=20 > >> replace > >> divide condition '(remainder * 2) / prate' with '(remainder * 2) >=3D = > >> prate' > >> > >> Fixes: f4973130d255 ("clk: qcom: clk-alpha-pll: Update set_rate for=20 > >> Zonda PLL") > >> Reported-by: Jon Hunter > >> Reported-by: kernel test robot > >> Reported-by: Dan Carpenter > >> Closes: https://lore.kernel.org/r/202408110724.8pqbpDiD-lkp@intel.com/ > >> Signed-off-by: Satya Priya Kakitapalli > >> --- > >> =C2=A0 drivers/clk/qcom/clk-alpha-pll.c | 4 +--- > >> =C2=A0 1 file changed, 1 insertion(+), 3 deletions(-) > >> > >> diff --git a/drivers/clk/qcom/clk-alpha-pll.c=20 > >> b/drivers/clk/qcom/clk-alpha-pll.c > >> index 019713c38f25..f9105443d7db 100644 > >> --- a/drivers/clk/qcom/clk-alpha-pll.c > >> +++ b/drivers/clk/qcom/clk-alpha-pll.c > >> @@ -2176,10 +2176,8 @@ static void zonda_pll_adjust_l_val(unsigned=20 > >> long rate, unsigned long prate, u32 > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 quotient =3D rate; > >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 remainder =3D do_div(quotient, prate); > >> -=C2=A0=C2=A0=C2=A0 *l =3D quotient; > >> -=C2=A0=C2=A0=C2=A0 if ((remainder * 2) / prate) > >> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *l =3D *l + 1; > >> +=C2=A0=C2=A0=C2=A0 *l =3D rate + (u32)(remainder * 2 >=3D prate); > >> =C2=A0 } > >> =C2=A0 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned l= ong=20 > >> rate, > >=20 > >=20 > > Tested-by: Jon Hunter >=20 >=20 > Looks like this has now landed in the mainline. Can we see if we can get = > this into v6.11? >=20 =20 Applied to clk-fixes. Was it too hard to keep the if statement and just change to a comparison? if (remainder * 2 >=3D prate) *l =3D *l + 1;