[PATCH v4 1/6] dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller

Barnabás Czémán
2025-03-15T14:58:17Z

Add device tree bindings for the global clock controller on Qualcomm
MSM8937 platform.

Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
---
.../bindings/clock/qcom,gcc-msm8937.yaml | 75 ++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8917.h | 17 +++++
2 files changed, 92 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8937.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8937.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..3c3f6756048e195671f542b3a6cd09057558eafa
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8937.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8937.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on MSM8937
+
+maintainers:
+ - Barnabas Czeman <barnabas.czeman@mainlining.org>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on MSM8937.
+
+ See also::
+ include/dt-bindings/clock/qcom,gcc-msm8917.h
+
+properties:
+ compatible:
+ const: qcom,gcc-msm8937
+
+ clocks:
+ items:
+ - description: XO source
+ - description: Sleep clock source
+ - description: DSI phy instance 0 dsi clock
+ - description: DSI phy instance 0 byte clock
+ - description: DSI phy instance 1 dsi clock
+ - description: DSI phy instance 1 byte clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+ - const: dsi0pll
+ - const: dsi0pllbyte
+ - const: dsi1pll
+ - const: dsi1pllbyte
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+
+ clock-controller@1800000 {
+ compatible = "qcom,gcc-msm8937";
+ reg = <0x01800000 0x80000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <&dsi0_phy 1>,
+ <&dsi0_phy 0>,
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>;
+ clock-names = "xo",
+ "sleep_clk",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "dsi1pll",
+ "dsi1pllbyte";
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h
index 4b421e7414b50bef2e2400f868ae5b7212a427bb..ec1f0b261dd5ccfe4896a00ffa9cf86de98b9cb3 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8917.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -170,6 +170,22 @@
#define VFE1_CLK_SRC 163
#define VSYNC_CLK_SRC 164
#define GPLL0_SLEEP_CLK_SRC 165
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 166
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 167
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 168
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 169
+#define BYTE1_CLK_SRC 170
+#define ESC1_CLK_SRC 171
+#define PCLK1_CLK_SRC 172
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 173
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 174
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 175
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 176
+#define GCC_MDSS_BYTE1_CLK 177
+#define GCC_MDSS_ESC1_CLK 178
+#define GCC_MDSS_PCLK1_CLK 179
+#define GCC_OXILI_AON_CLK 180
+#define GCC_OXILI_TIMER_CLK 181

/* GCC block resets */
#define GCC_CAMSS_MICRO_BCR 0
@@ -187,5 +203,6 @@
#define VENUS_GDSC 5
#define VFE0_GDSC 6
#define VFE1_GDSC 7
+#define OXILI_CX_GDSC 8

#endif

--
2.48.1