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([2001:a61:34c9:ea01:14b4:7ed9:5135:9381]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cb66a6d0besm5680417a12.57.2024.10.24.05.35.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2024 05:35:38 -0700 (PDT) Message-ID: <1e0097f6a15f47c173cb207e369909c1cb5943f9.camel@gmail.com> Subject: Re: [PATCH 1/2] dt-bindings: clock: axi-clkgen: include AXI clk From: Nuno =?ISO-8859-1?Q?S=E1?= To: Conor Dooley , Nuno Sa Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lars-Peter Clausen Date: Thu, 24 Oct 2024 14:35:37 +0200 In-Reply-To: <20241023-tucking-pacific-7360480bcb61@spud> References: <20241023-axi-clkgen-fix-axiclk-v1-0-980a42ba51c3@analog.com> <20241023-axi-clkgen-fix-axiclk-v1-1-980a42ba51c3@analog.com> <20241023-tucking-pacific-7360480bcb61@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-10-23 at 17:30 +0100, Conor Dooley wrote: > On Wed, Oct 23, 2024 at 04:56:54PM +0200, Nuno Sa wrote: > > In order to access the registers of the HW, we need to make sure that > > the AXI bus clock is enabled. Hence let's increase the number of clocks > > by one. > >=20 > > In order to keep backward compatibility, the new axi clock must be the > > last phandle in the array. To make the intent clear, a non mandatory > > clock-names property is also being added. >=20 > Hmm, I'm not sure. I think clock-names actually may need to be mandatory > here, as otherwise you'll not what the second clock is. The driver would > have to interpret no clock-names meaning clock 2 was clkin2. >=20 >=20 So the way things are now is that we just get the parents count with of_clk_get_parent_count() and then get the names with of_clk_get_parent_nam= e() and this is given into 'struct clk_init_data'. So they are effectively clk_pare= nts of the clock we're registering and as you can see clock-names does not really matt= er. What I'm trying to do is to keep this and still allow to get the AXI bus clock w= hich is something we should get and enable and not rely on others to do it. The ide= a is then to add the axi bus clock as the last one in the clocks property and I will = get it by index with of_clk_get(). The rest pretty much remains the same and we just = need to decrement by one the number of parent clocks as the axi clock is not really= a parent of our output clock. All that said, and FWIW, clock-names are not even being used in the driver.= I just added it to the bindings to make the intent clear. I could have it in the d= river but I'm not sure the extra complexity would be worth it... - Nuno S=C3=A1