From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
To: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, lee@kernel.org,
mturquette@baylibre.com, sboyd@kernel.org,
jassisinghbrar@gmail.com, catalin.marinas@arm.com,
will@kernel.org, shawnguo@kernel.org, arnd@arndb.de,
marcel.ziswiler@toradex.com, robimarko@gmail.com,
dmitry.baryshkov@linaro.org, nfraprado@collabora.com,
broonie@kernel.org, quic_gurus@quicinc.com,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: quic_srichara@quicinc.com, quic_gokulsri@quicinc.com,
quic_sjaganat@quicinc.com, quic_kathirav@quicinc.com,
quic_arajkuma@quicinc.com, quic_anusha@quicinc.com,
quic_devipriy@quicinc.com
Subject: Re: [PATCH V4 5/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode
Date: Wed, 15 Feb 2023 15:17:48 +0000 [thread overview]
Message-ID: <1e26211a-c8eb-5f2f-9f55-c3d3ebc76b94@linaro.org> (raw)
In-Reply-To: <b5135d69-3783-8147-bda5-8131cea726f7@quicinc.com>
On 15/02/2023 10:55, POOVENDHAN SELVARAJ wrote:
>
> On 2/14/2023 6:27 PM, Srinivas Kandagatla wrote:
>>
>>
>> On 14/02/2023 05:14, Poovendhan Selvaraj wrote:
>>> CrashDump collection is based on the DLOAD bit of TCSR register.
>>> To retain other bits, we read the register and modify only the DLOAD
>>> bit as
>>> the other bits have their own significance.
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
>>> ---
>>> Changes in V4:
>>> - retain the orginal value of tcsr register when download mode
>>> is not set
>>>
>>> drivers/firmware/qcom_scm.c | 15 ++++++++++-----
>>> 1 file changed, 10 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
>>> index 468d4d5ab550..8a34b386ac3a 100644
>>> --- a/drivers/firmware/qcom_scm.c
>>> +++ b/drivers/firmware/qcom_scm.c
>>> @@ -407,7 +407,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id)
>>> }
>>> EXPORT_SYMBOL(qcom_scm_set_remote_state);
>>> -static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
>>> +static int __qcom_scm_set_dload_mode(struct device *dev, u32 val,
>>> bool enable)
>>> {
>>> struct qcom_scm_desc desc = {
>>> .svc = QCOM_SCM_SVC_BOOT,
>>> @@ -417,7 +417,8 @@ static int __qcom_scm_set_dload_mode(struct
>>> device *dev, bool enable)
>>> .owner = ARM_SMCCC_OWNER_SIP,
>>> };
>>> - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
>>> + desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE :
>>> + val & ~(QCOM_SCM_BOOT_SET_DLOAD_MODE);
>>
>> why not read the value here before setting the DLOAD Mode instead of
>> doing it in qcom_scm_set_download_mode()?
>> that would make the code simple and readable.
>
> dload_addr_val is used in both if and else if cases in
> qcom_scm_set_download_mode(), so we read in qcom_scm_set_download_mode()
> function and pass to __qcom_scm_set_dload_mode().
that is fine as it is, I missread else part as calling
__qcom_scm_set_dload_mode() too.
just check the ret value should be good.
--srini
>
> if (avail) {
> - ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
> *+ ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val,
> enable); *
> } else if (__scm->dload_mode_addr) {
> - ret = qcom_scm_io_writel(__scm->dload_mode_addr,
> - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
> + ret = qcom_scm_io_writel(__scm->dload_mode_addr, enable ?
> + * dload_addr_val | QCOM_SCM_BOOT_SET_DLOAD_MODE : **
> **+ dload_addr_val & ~(QCOM_SCM_BOOT_SET_DLOAD_MODE)); *
> } else {
>
>>
>>> return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
>>> }
>>> @@ -426,15 +427,19 @@ static void qcom_scm_set_download_mode(bool
>>> enable)
>>> {
>>> bool avail;
>>> int ret = 0;
>>> + u32 dload_addr_val;
>>> avail = __qcom_scm_is_call_available(__scm->dev,
>>> QCOM_SCM_SVC_BOOT,
>>> QCOM_SCM_BOOT_SET_DLOAD_MODE);
>>> + ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val);
>>> +
>> not checking ret value here before proceeding?
>>
> Okay, sure..will address in next patch series.
>>> if (avail) {
>>> - ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
>>> + ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val,
>>> enable);
>>> } else if (__scm->dload_mode_addr) {
>>> - ret = qcom_scm_io_writel(__scm->dload_mode_addr,
>>> - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
>>> + ret = qcom_scm_io_writel(__scm->dload_mode_addr, enable ?
>>> + dload_addr_val | QCOM_SCM_BOOT_SET_DLOAD_MODE :
>>> + dload_addr_val & ~(QCOM_SCM_BOOT_SET_DLOAD_MODE));
>>> } else {
>>> dev_err(__scm->dev,
>>> "No available mechanism for setting download mode\n");
>
> Regards,
> Poovendhan S
>
next prev parent reply other threads:[~2023-02-15 15:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 5:14 [PATCH V4 0/5] Enable crashdump collection support for IPQ9574 Poovendhan Selvaraj
2023-02-14 5:14 ` [PATCH V4 1/5] dt-bindings: scm: Add compatible " Poovendhan Selvaraj
2023-02-14 7:54 ` Krzysztof Kozlowski
2023-02-14 5:14 ` [PATCH V4 2/5] dt-bindings: mfd: Add the tcsr " Poovendhan Selvaraj
2023-02-14 5:14 ` [PATCH V4 3/5] arm64: dts: qcom: ipq9574: Enable the download mode support Poovendhan Selvaraj
2023-02-14 5:14 ` [PATCH V4 4/5] arm64: dts: qcom: ipq9574: Add SMEM support Poovendhan Selvaraj
2023-02-14 7:54 ` Krzysztof Kozlowski
2023-02-14 5:14 ` [PATCH V4 5/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode Poovendhan Selvaraj
2023-02-14 12:57 ` Srinivas Kandagatla
[not found] ` <b5135d69-3783-8147-bda5-8131cea726f7@quicinc.com>
2023-02-15 15:17 ` Srinivas Kandagatla [this message]
2023-02-15 2:34 ` [PATCH V4 0/5] Enable crashdump collection support for IPQ9574 Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1e26211a-c8eb-5f2f-9f55-c3d3ebc76b94@linaro.org \
--to=srinivas.kandagatla@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=arnd@arndb.de \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=jassisinghbrar@gmail.com \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=lee@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marcel.ziswiler@toradex.com \
--cc=mturquette@baylibre.com \
--cc=nfraprado@collabora.com \
--cc=quic_anusha@quicinc.com \
--cc=quic_arajkuma@quicinc.com \
--cc=quic_devipriy@quicinc.com \
--cc=quic_gokulsri@quicinc.com \
--cc=quic_gurus@quicinc.com \
--cc=quic_kathirav@quicinc.com \
--cc=quic_poovendh@quicinc.com \
--cc=quic_sjaganat@quicinc.com \
--cc=quic_srichara@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=robimarko@gmail.com \
--cc=sboyd@kernel.org \
--cc=shawnguo@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox