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Tue, 04 Nov 2025 02:14:57 -0800 (PST) From: Jerome Brunet To: Jian Hu Cc: Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , Stephen Boyd , Michael Turquette , Dmitry Rokosov , robh+dt , Rob Herring , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: Re: [PATCH v4 5/5] clk: meson: t7: add t7 clock peripherals controller driver In-Reply-To: <3b9a5978-aa02-486b-85f5-6443dc607dd5@amlogic.com> (Jian Hu's message of "Tue, 4 Nov 2025 17:17:50 +0800") References: <20251030094345.2571222-1-jian.hu@amlogic.com> <20251030094345.2571222-6-jian.hu@amlogic.com> <1jbjlnxuug.fsf@starbuckisacylon.baylibre.com> <3b9a5978-aa02-486b-85f5-6443dc607dd5@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 04 Nov 2025 11:14:57 +0100 Message-ID: <1j1pmew1cu.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Tue 04 Nov 2025 at 17:17, Jian Hu wrote: >>> + >>> +static struct clk_regmap t7_dspa =3D { >>> + .data =3D &(struct clk_regmap_mux_data){ >>> + .offset =3D DSPA_CLK_CTRL0, >>> + .mask =3D 0x1, >>> + .shift =3D 15, >>> + }, >>> + .hw.init =3D &(struct clk_init_data){ >>> + .name =3D "dspa", >>> + .ops =3D &clk_regmap_mux_ops, >>> + .parent_hws =3D (const struct clk_hw *[]) { >>> + &t7_dspa_a.hw, >>> + &t7_dspa_b.hw, >>> + }, >>> + .num_parents =3D 2, >>> + .flags =3D CLK_SET_RATE_PARENT, >>> + }, >>> +}; >>> + >>> ...... >>> + >>> +static struct clk_regmap t7_anakin_0 =3D { >> Nitpick: for the DSP it was a/b, here it is 0/1 >> Could you pick one way or the other and stick to it ? > > > ok , I will use 0/1 for DSP. I think I prefer a/b if you don't mind. see below for why ... > >>> + .data =3D &(struct clk_regmap_gate_data){ >>> + .offset =3D ANAKIN_CLK_CTRL, >>> + .bit_idx =3D 8, >>> + }, >>> + .hw.init =3D &(struct clk_init_data) { >>> + .name =3D "anakin_0", >>> + .ops =3D &clk_regmap_gate_ops, >>> + .parent_hws =3D (const struct clk_hw *[]) { &t7_anakin_0_= div.hw }, >>> + .num_parents =3D 1, >>> + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, >>> + }, >>> +}; [...] >>> + >>> +static struct clk_regmap t7_anakin_clk =3D { >>> + .data =3D &(struct clk_regmap_gate_data){ >>> + .offset =3D ANAKIN_CLK_CTRL, >>> + .bit_idx =3D 30, >>> + }, >>> + .hw.init =3D &(struct clk_init_data) { >>> + .name =3D "anakin_clk", >> Again, not a great name, especially considering the one above. >> Is this really really how the doc refers to these 2 clocks ? > > > bit30 gate clock is after bit31 mux clock,=C2=A0 and the gate clock is th= e final > output clock, it is used to gate anakin clock. > > I will rename bit31 as anakin_pre, rename bit30 as anakin. Ok for the last element ... but I don't like "_pre" for a mux selecting one the 2 glitch free path. It does not help understanding the tree. For such mux, when it is not the last element, I would suggest "_ab_sel" ... at least it is clear what it does so, "anakin_ab_sel" ? > >>> + .ops =3D &clk_regmap_gate_ops, >>> + .parent_hws =3D (const struct clk_hw *[]) { >>> + &t7_anakin.hw >>> + }, >>> + .num_parents =3D 1, >>> + .flags =3D CLK_SET_RATE_PARENT >>> + }, >>> +}; >>> +