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AJvYcCWO1qKd7pZO9qoqJEztVUmB3UII+Kz1CNqBIYEbFTAstPWPsJW2U+oRkOuMGwgXrB6LakMB0M01bjk=@vger.kernel.org X-Gm-Message-State: AOJu0YwtbbFs8bmkmk6NAfdszArH03SUaCabLx0mziraUJPoX87XbG+9 KkNkWgrIXfxrHQtKzTHhxOe0iIu/HysxBVdH85UwzdT1OWy43sw4xYaIZtAAPNIj/qiAAOc5J7/ 6 X-Google-Smtp-Source: AGHT+IEAQ8+ZbApQ3oMw8V0g6qInfVZypTuRChEdnmRNkaOEzMCP4G/akqQASSKuY+whN0GPsSSR7g== X-Received: by 2002:adf:ea09:0:b0:374:c1be:bf2e with SMTP id ffacd0b85a97d-374c1bec8ecmr12950003f8f.62.1725605476525; Thu, 05 Sep 2024 23:51:16 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:4e33:801c:cee0:ee57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ca05c6facsm10144635e9.9.2024.09.05.23.51.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 23:51:16 -0700 (PDT) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , chuan.liu@amlogic.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] clk: meson: Support PLL with fixed fractional denominators In-Reply-To: <20240906-fix_clk-v1-1-2977ef0d72e7@amlogic.com> (Chuan Liu via's message of "Fri, 06 Sep 2024 13:52:33 +0800") References: <20240906-fix_clk-v1-0-2977ef0d72e7@amlogic.com> <20240906-fix_clk-v1-1-2977ef0d72e7@amlogic.com> Date: Fri, 06 Sep 2024 08:51:15 +0200 Message-ID: <1j34mds2ak.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri 06 Sep 2024 at 13:52, Chuan Liu via B4 Relay wrote: > From: Chuan Liu > > Some PLLs with fractional multipliers have fractional denominators that > are fixed to "100000" instead of the previous "(1 << pll->frac.width)". > > Signed-off-by: Chuan Liu > --- > drivers/clk/meson/clk-pll.c | 22 +++++++++++++++++++--- > drivers/clk/meson/clk-pll.h | 1 + > 2 files changed, 20 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index bc570a2ff3a3..f0009c174564 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c > @@ -36,6 +36,12 @@ > #include "clk-regmap.h" > #include "clk-pll.h" > > +/* > + * Some PLLs with fractional multipliers have fractional denominators that > + * are fixed to "100000" instead of the previous "(1 << pll->frac.width)". > + */ > +#define FIXED_FRAC_MAX 100000 When the next arbitrary limit comes around, this will get very ugly. Instead, please add frac_max to the pll parameter > + > static inline struct meson_clk_pll_data * > meson_clk_pll_data(struct clk_regmap *clk) > { > @@ -57,12 +63,17 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate, > struct meson_clk_pll_data *pll) > { > u64 rate = (u64)parent_rate * m; > + unsigned int frac_max; > > if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { > u64 frac_rate = (u64)parent_rate * frac; > > - rate += DIV_ROUND_UP_ULL(frac_rate, > - (1 << pll->frac.width)); > + if (pll->flags & CLK_MESON_PLL_FIXED_FRAC_MAX) > + frac_max = FIXED_FRAC_MAX; > + else > + frac_max = (1 << pll->frac.width); > + > + rate += DIV_ROUND_UP_ULL(frac_rate, frac_max); > } > > return DIV_ROUND_UP_ULL(rate, n); > @@ -100,13 +111,18 @@ static unsigned int __pll_params_with_frac(unsigned long rate, > unsigned int n, > struct meson_clk_pll_data *pll) > { > - unsigned int frac_max = (1 << pll->frac.width); > + unsigned int frac_max; > u64 val = (u64)rate * n; > > /* Bail out if we are already over the requested rate */ > if (rate < parent_rate * m / n) > return 0; > > + if (pll->flags & CLK_MESON_PLL_FIXED_FRAC_MAX) Certainly don't need a flag for that. Use a parameter and default to (1 << pll->frac.width) if unset. > + frac_max = FIXED_FRAC_MAX; > + else > + frac_max = (1 << pll->frac.width); > + > if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) > val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate); > else > diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h > index 7b6b87274073..e996d3727eb1 100644 > --- a/drivers/clk/meson/clk-pll.h > +++ b/drivers/clk/meson/clk-pll.h > @@ -29,6 +29,7 @@ struct pll_mult_range { > > #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) > #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1) > +#define CLK_MESON_PLL_FIXED_FRAC_MAX BIT(2) Remove this. > > struct meson_clk_pll_data { > struct parm en; -- Jerome