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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a01fa137basm53110945e9.1.2026.10.01.02.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 02:44:33 -0700 (PDT) From: Jerome Brunet To: Miquel Raynal , Jacky Huang , Shan-Chun Hung , Michael Turquette , Stephen Boyd , Richard Cochran , Arnd Bergmann , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Thomas Petazzoni , Steam Lin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Miquel Raynal , Jacky Huang , stable@vger.kernel.org Subject: Re: [PATCH v6 05/12] clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks In-Reply-To: <20260930-perso-ma35d1-upstream-clk-v6-5-48937ee6c9bb@bootlin.com> References: <20260930-perso-ma35d1-upstream-clk-v6-0-48937ee6c9bb@bootlin.com> <20260930-perso-ma35d1-upstream-clk-v6-5-48937ee6c9bb@bootlin.com> Date: Thu, 01 Oct 2026 11:44:32 +0200 Message-ID: <1j4if53gcf.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On mer. 30 sept. 2026 at 19:24, Miquel Raynal wrote: > The WDT and WWDT muxes list PCLK3/4096 and PCLK4/4096 among their > possible parents, but the driver never registers the corresponding > clocks, so these parents could never be used. > > Add pclk3_div4096 and pclk4_div4096 as fixed factor children of pclk3 > and pclk4 and expose them through the clock provider. > > Reported-by: Jacky Huang > Closes: https://lore.kernel.org/linux-clk/b8a8a65b-e302-4747-bc90-4920fc48795a@gmail.com/ > Suggested-by: Jacky Huang > Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") > Cc: stable@vger.kernel.org > Link: https://lore.kernel.org/linux-clk/b8a8a65b-e302-4747-bc90-4920fc48795a@gmail.com/ Is this is a mistake ? We usually add this when applying > Reviewed-by: Jerome Brunet > Signed-off-by: Miquel Raynal > --- > drivers/clk/nuvoton/clk-ma35d1.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c > index 6aa42a3e1be3..c914079cee2d 100644 > --- a/drivers/clk/nuvoton/clk-ma35d1.c > +++ b/drivers/clk/nuvoton/clk-ma35d1.c > @@ -17,7 +17,7 @@ > static DEFINE_SPINLOCK(ma35d1_lock); > > #define PLL_MAX_NUM 5 > -#define MA35D1_CLK_COUNT 236 > +#define MA35D1_CLK_COUNT 238 > > /* Clock Control Registers Offset */ > #define REG_CLK_PWRCTL 0x00 > @@ -544,6 +544,8 @@ static int ma35d1_clocks_probe(struct platform_device *pdev) > hws[HCLK3] = ma35d1_clk_fixed_factor(dev, "hclk3", "sysclk1_mux", 1, 2); > hws[PCLK3] = ma35d1_clk_fixed_factor(dev, "pclk3", "sysclk1_mux", 1, 2); > hws[PCLK4] = ma35d1_clk_fixed_factor(dev, "pclk4", "sysclk1_mux", 1, 2); > + hws[PCLK3_DIV4096] = ma35d1_clk_fixed_factor(dev, "pclk3_div4096", "pclk3", 1, 4096); > + hws[PCLK4_DIV4096] = ma35d1_clk_fixed_factor(dev, "pclk4_div4096", "pclk4", 1, 4096); > > hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); > hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000); > > -- > 2.55.0 > -- Jerome