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Fri, 31 Oct 2025 09:27:58 -0700 (PDT) From: Jerome Brunet To: Chuan Liu Cc: Chuan Liu via B4 Relay , Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/4] clk: amlogic: optimize the PLL driver In-Reply-To: <9751014d-926e-4d42-b8e1-5a4d3e734457@amlogic.com> (Chuan Liu's message of "Fri, 31 Oct 2025 23:09:13 +0800") References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> <1jms57xx05.fsf@starbuckisacylon.baylibre.com> <9751014d-926e-4d42-b8e1-5a4d3e734457@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Fri, 31 Oct 2025 17:27:58 +0100 Message-ID: <1j5xbvxchd.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri 31 Oct 2025 at 23:09, Chuan Liu wrote: > Hi Jerome, > > On 10/31/2025 5:04 PM, Jerome Brunet wrote: >> [ EXTERNAL EMAIL ] >> On Fri 31 Oct 2025 at 16:10, Chuan Liu via B4 Relay >> wrote: >>=20 >>> This patch series consists of four topics involving the amlogic PLL >>> driver: >>> - Fix out-of-range PLL frequency setting. >>> - Improve the issue of PLL lock failures. >>> - Add handling for PLL lock failure. >>> - Optimize PLL enable timing. >>> >>> For easier review and management, these are submitted as a single >>> patch series. >>> >>> The PLL timing optimization changes were merged into our internal >>> repository quite some time ago and have been verified on a large >>> number of SoCs: >>> - Already supported upstream: G12A, G12B, SM1, S4, A1, C3. >>> - Planned for upstream support: T7, A5, A4, S7, S7D, S6, etc. >>> >>> Based on the upstream code base, I have performed functional testing >>> on G12A, A1, A5, A4, T7, S7, S7D, and S6, all of which passed. >>> >>> Additionally, stress testing using scripts was conducted on A5 and >>> A1, with over 40,000 and 50,000 iterations respectively, and no >>> abnormalities were observed. Below is a portion of the stress test >>> log (CLOCK_ALLOW_WRITE_DEBUGFS has been manually enabled): >> Okay, this little game has been going on long enough. >> You've posted v2 24h hours ago >> You've got feedback within hours >> There was still a 1 question pending >> The rest of community had no chance to review. >>=20 > > There might be a serious misunderstanding here. > > In recent years, we've mainly been maintaining our code in our > internal repository, which has led to some differences between our > internal codebase and the upstream version. The patches that account > for these differences are already queued for submission, and several > SoCs are also waiting in line to be submitted. As a result, quite a > few patches have piled up, waiting to go upstream. > > Previously, I had been waiting for your clock driver restructuring > patches to be ready (which have recently been merged), so for almost > a year, we haven't made much progress on clock driver=E2=80=93related > upstreaming. Ohoh now you are just teasing me ! That work was made necessary because of all the copy/paste Amlogic was submitting. Despite many requests, this was never addressed so I had to step in. If you want things to go faster, then *really* pay attention to the review you are getting, do not ask question to ignore the answers and stop making people repeat themselves over and over.