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[90.182.211.1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a162e867e8sm325870355e9.15.2026.10.05.07.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2026 07:27:39 -0700 (PDT) From: Jerome Brunet To: Vyacheslav Yurkov via B4 Relay , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Brian Masney , Brian Masney , Jerome Brunet , Jyri Sarha Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Vyacheslav Yurkov , Vyacheslav Yurkov Subject: Re: [PATCH v8 1/2] dt-bindings: clock: gpio-gate-clock: Add a new compatible string In-Reply-To: <20260927-feature-clock-guard-v8-1-630938e302a1@bruker.com> References: <20260927-feature-clock-guard-v8-0-630938e302a1@bruker.com> <20260927-feature-clock-guard-v8-1-630938e302a1@bruker.com> Date: Mon, 05 Oct 2026 16:27:37 +0200 Message-ID: <1jbj986x46.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Sun 27 Sep 2026 at 14:59, Vyacheslav Yurkov via B4 Relay wrote: > From: Vyacheslav Yurkov > > Extend the binding to be used also for gpio-locked-fixed-clock. > A GPIO-locked fixed clock provider exposes a fixed-rate clock whose > availability depends on one or more GPIO lock-status signals. > > Some hardware designs provide fixed-frequency clocks generated outside > software control, such as by FPGA-resident PLLs. While the clock rate is > fixed, a separate GPIO signal indicates whether the clock source is > locked and producing a valid output. > > Signed-off-by: Vyacheslav Yurkov > --- > .../devicetree/bindings/clock/gpio-gate-clock.yaml | 32 ++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml > index d09d0e3f0c6e..1ad87c8b36b9 100644 > --- a/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml > +++ b/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml > @@ -11,7 +11,9 @@ maintainers: > > properties: > compatible: > - const: gpio-gate-clock > + enum: > + - gpio-gate-clock > + - gpio-locked-clock I think this name does not illustrate well what your driver does anymore. As I noted before, locked if very much PLL centric. enabled ? While the driver sits in the same C file (clk-gpio), I don't the binding doc should. I'll defer to the DT folks on this but I think it would more approriate with a different yaml. clk-gpio-gate and clk-gpio-mux have their own binding doc > > clocks: > maxItems: 1 > @@ -23,10 +25,29 @@ properties: > description: GPIO reference for enabling and disabling the clock. > maxItems: 1 > > + enabled-gpios: > + description: GPIO that indicates whether the clock is enabled or disabled. > + maxItems: 1 > + > required: > - compatible > - '#clock-cells' > - - enable-gpios > + > +allOf: > + - if: > + properties: > + compatible: > + const: gpio-gate-clock > + then: > + required: > + - enable-gpios > + - if: > + properties: > + compatible: > + const: gpio-locked-clock I think there should be a property in here to express how long you are willing to wait for the clock to be enabled. IOW the lock timeout. > + then: > + required: > + - enabled-gpios > > additionalProperties: false > > @@ -40,3 +61,10 @@ examples: > #clock-cells = <0>; > enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; > }; > + > + clk_gpio_locked { > + compatible = "gpio-locked-clock"; > + #clock-cells = <0>; > + clocks = <&pll>; > + enabled-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; > + }; > > -- > 2.34.1 > > -- Jerome