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[82.65.169.74]) by smtp.gmail.com with ESMTPSA id u7-20020a05600c19c700b0038cc9aac1a3sm18656708wmq.23.2022.04.11.01.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 01:36:31 -0700 (PDT) References: <20220408091037.2041955-1-maxime@cerno.tech> <20220408091037.2041955-23-maxime@cerno.tech> <1jwnfzlxx1.fsf@starbuckisacylon.baylibre.com> <20220408104127.ilmcntbhvktr2fbh@houat> <1jpmlrlq0h.fsf@starbuckisacylon.baylibre.com> <20220408125526.ykk5ktix52mnwvh2@houat> <1jlewflizh.fsf@starbuckisacylon.baylibre.com> <20220408153625.ugodcmfwtanr75gu@houat> User-agent: mu4e 1.6.10; emacs 27.1 From: Jerome Brunet To: Maxime Ripard Cc: Mike Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Naresh Kamboju , Alexander Stein , Marek Szyprowski , Tony Lindgren , Yassine Oudjana , Neil Armstrong Subject: Re: [PATCH 22/22] clk: Prevent a clock without a rate to register Date: Mon, 11 Apr 2022 10:20:51 +0200 In-reply-to: <20220408153625.ugodcmfwtanr75gu@houat> Message-ID: <1jczhoauen.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Fri 08 Apr 2022 at 17:36, Maxime Ripard wrote: > > You're confusing two things: the rate output by the hardware, and what > the CCF needs to return. We're discussing the latter here, a software > construct. It models the hardware, but it doesn't have to be true to the > hardware. > > And even the meson driver doesn't follow what you're claiming to the > letter and is inconsistent with what you're saying. Any disabled gate > will also have a hardware rate of 0. Yet, it doesn't return 0 in such a > case. And no one does, because clk_get_rate() isn't supposed to return > the actual rate in hardware at the moment. It's supposed to return what > would be the rate if it was enabled. I don't think I am confused at all. What rate would you get if you would hit enable on those PLLs with the invalid setting as they are ? 0 - no lock. recalc_rate() is about giving the rate of the clock based on its current parameters. This is exactly what the amlogic PLL driver does. I can't compute a division by zero, sorry. The fact that some parameters may be invalid for a clock element is not specific to any SoC and we have to deal with it. It is not up to the clock driver to select a random rate to just to make that valid again, assuming it even can do so which is not necessarily the case.