Re: [PATCH V3 4/6] dt-bindings: clk: meson: add S4 SoC peripheral clock controller bindings

Krzysztof Kozlowski
2022-08-05T09:16:06Z

On 05/08/2022 10:57, Yu Tu wrote:
> Add peripheral clock controller compatible and dt-bindings header for
> the of the S4 SoC.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> .../bindings/clock/amlogic,s4-clkc.yaml | 92 ++++++++++++
> include/dt-bindings/clock/amlogic,s4-clkc.h | 131 ++++++++++++++++++
> 2 files changed, 223 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml
> create mode 100644 include/dt-bindings/clock/amlogic,s4-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml
> new file mode 100644
> index 000000000000..2471276afda9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml

Filename should be based on compatible, so amlogic,s4-periphs-clkc.yaml

> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,s4-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic Meson S serials Peripheral Clock Controller Device Tree Bindings

s/Device Tree Bindings//

> +
> +maintainers:
> + - Neil Armstrong <narmstrong@baylibre.com>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Yu Tu <yu.hu@amlogic.com>
> +
> +
> +properties:
> + compatible:
> + const: amlogic,s4-periphs-clkc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: input fixed pll div2
> + - description: input fixed pll div2p5
> + - description: input fixed pll div3
> + - description: input fixed pll div4
> + - description: input fixed pll div5
> + - description: input fixed pll div7
> + - description: input hifi pll
> + - description: input gp0 pll
> + - description: input mpll0
> + - description: input mpll1
> + - description: input mpll2
> + - description: input mpll3
> + - description: input hdmi pll
> + - description: input oscillator (usually at 24MHz)
> +
> + clock-names:
> + items:
> + - const: fclk_div2
> + - const: fclk_div2p5
> + - const: fclk_div3
> + - const: fclk_div4
> + - const: fclk_div5
> + - const: fclk_div7
> + - const: hifi_pll
> + - const: gp0_pll
> + - const: mpll0
> + - const: mpll1
> + - const: mpll2
> + - const: mpll3
> + - const: hdmi_pll
> + - const: xtal
> +
> + "#clock-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clkc_periphs: periphs-clock-controller@fe000000 {
> + compatible = "amlogic,s4-periphs-clkc";
> + reg = <0xfe000000 0x49c>;
> + clocks = <&clkc_pll 3>,
> + <&clkc_pll 13>,
> + <&clkc_pll 5>,
> + <&clkc_pll 7>,
> + <&clkc_pll 9>,
> + <&clkc_pll 11>,
> + <&clkc_pll 17>,
> + <&clkc_pll 15>,
> + <&clkc_pll 25>,
> + <&clkc_pll 27>,
> + <&clkc_pll 29>,
> + <&clkc_pll 31>,
> + <&clkc_pll 20>,
> + <&xtal>;
> + clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
> + "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
> + "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";
> + #clock-cells = <1>;
> + };
> +...
> diff --git a/include/dt-bindings/clock/amlogic,s4-clkc.h b/include/dt-bindings/clock/amlogic,s4-clkc.h
> new file mode 100644
> index 000000000000..d203b9bbf29e
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,s4-clkc.h

Probably this should be then amlogic,s4-periphs-clkc.h

> @@ -0,0 +1,131 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
> +#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H

Best regards,
Krzysztof