Re: [PATCH V3 3/6] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Yu Tu
2022-08-30T06:08:08Z

On 2022/8/29 17:46, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
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> On Mon 15 Aug 2022 at 14:34, Yu Tu <yu.tu@amlogic.com> wrote:
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>> Hi Jerome,
>>
>> On 2022/8/10 21:47, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>> On Fri 05 Aug 2022 at 16:57, Yu Tu <yu.tu@amlogic.com> wrote:
>>> */
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> [... ]
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>>>> +#define ANACTRL_FIXPLL_CTRL0 (0x0010 << 2)
>>> I already commented on the "<< 2" . Remove them please.
>> Sorry, maybe I didn't pay attention to this comment earlier. A little bit
>> of a question why is this not okay? I understand isn't it better for the
>> compiler to help with this calculation itself?
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> Because it is aweful to read
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> Also please trim your replies.
> It is a bit annoying to search for your comments in the replies
>

Okay. Like this?

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