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AJvYcCWf2nfdEoOb3A8ieoouEDN/CcYlcWMmbKF6nDWJiUal6nEtkGIASXqLupkiQeGF6yerRaJL4dUP4hw=@vger.kernel.org X-Gm-Message-State: AOJu0YxKZi8Q+RWHkSIUGpnz+7Gj1BM/LgQNDHS1LheX1IxhVwdlD4Zn fFwS0Qn888ZG8Ye79T1mMGeJCB8vu5fBmJU9jggDY0wq3fazN+B2VXfUv/UH+Os= X-Google-Smtp-Source: AGHT+IFj6cn2VhPIBLzycX7f8yDdpZxCP0fnyLUp+RAmxAnbmLYkKHqCh+9DjZxSWH8mgvyVVR5CDA== X-Received: by 2002:adf:cd0d:0:b0:371:93eb:78a4 with SMTP id ffacd0b85a97d-378895c5b22mr1505513f8f.9.1725621778667; Fri, 06 Sep 2024 04:22:58 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:b0ad:b504:10d4:481d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-374b34725desm18835563f8f.81.2024.09.06.04.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 04:22:58 -0700 (PDT) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , chuan.liu@amlogic.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/3] clk: meson: Support PLL with fixed fractional denominators In-Reply-To: <20240906-fix_clk-v2-1-7a3941eb2cdf@amlogic.com> (Chuan Liu via's message of "Fri, 06 Sep 2024 18:34:40 +0800") References: <20240906-fix_clk-v2-0-7a3941eb2cdf@amlogic.com> <20240906-fix_clk-v2-1-7a3941eb2cdf@amlogic.com> Date: Fri, 06 Sep 2024 13:22:57 +0200 Message-ID: <1jjzfpqb5a.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri 06 Sep 2024 at 18:34, Chuan Liu via B4 Relay wrote: > From: Chuan Liu > > Some PLLS with fractional multipliers have fractional denominators with > fixed values, instead of the previous "(1 << pll-> frc.width)". > > Signed-off-by: Chuan Liu > --- > drivers/clk/meson/clk-pll.c | 8 +++++--- > drivers/clk/meson/clk-pll.h | 1 + > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index bc570a2ff3a3..a141ab450009 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c > @@ -57,12 +57,13 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate, > struct meson_clk_pll_data *pll) > { > u64 rate = (u64)parent_rate * m; > + unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max > : ^ Please don't play with this unless you've got justification a for it. By justification, I mean actual numbers showing the difference it makes and not just for the platforms listed in this series, but all the platforms supported by this driver. > + (1 << pll->frac.width); > > if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { > u64 frac_rate = (u64)parent_rate * frac; > > - rate += DIV_ROUND_UP_ULL(frac_rate, > - (1 << pll->frac.width)); > + rate += DIV_ROUND_UP_ULL(frac_rate, frac_max); > } > > return DIV_ROUND_UP_ULL(rate, n); > @@ -100,7 +101,8 @@ static unsigned int __pll_params_with_frac(unsigned long rate, > unsigned int n, > struct meson_clk_pll_data *pll) > { > - unsigned int frac_max = (1 << pll->frac.width); > + unsigned int frac_max = unlikely(pll->frac_max) ? pll->frac_max : > + (1 << pll->frac.width); > u64 val = (u64)rate * n; > > /* Bail out if we are already over the requested rate */ > diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h > index 7b6b87274073..949157fb7bf5 100644 > --- a/drivers/clk/meson/clk-pll.h > +++ b/drivers/clk/meson/clk-pll.h > @@ -43,6 +43,7 @@ struct meson_clk_pll_data { > unsigned int init_count; > const struct pll_params_table *table; > const struct pll_mult_range *range; > + unsigned int frac_max; > u8 flags; > }; -- Jerome