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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id a23-20020a05600c225700b003cfe1376f68sm8168690wmm.9.2022.12.02.04.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 04:07:06 -0800 (PST) References: <20221201225703.6507-1-ddrokosov@sberdevices.ru> <20221201225703.6507-12-ddrokosov@sberdevices.ru> User-agent: mu4e 1.8.10; emacs 28.2 From: Jerome Brunet To: Dmitry Rokosov , neil.armstrong@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Cc: jian.hu@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 11/11] arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers Date: Fri, 02 Dec 2022 13:03:59 +0100 In-reply-to: <20221201225703.6507-12-ddrokosov@sberdevices.ru> Message-ID: <1jlenq6mc7.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Fri 02 Dec 2022 at 01:57, Dmitry Rokosov wrote: > This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi. > The first one clk controller is responsible for all SoC peripherals > clocks excluding audio clocks. The second one clk controller is used by > A1 SoC PLLs. Actually, there are two different APB heads, so we have two > different drivers. Please send this change through a separate patcheset. One patcheset/series for clk (and bindings) Another one for the DTS (usually sent after the first one is accepted) > > Signed-off-by: Dmitry Rokosov > --- > arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > index b4000cf65a9a..38e6517c603c 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > @@ -6,6 +6,8 @@ > #include > #include > #include > +#include > +#include > > / { > compatible = "amlogic,a1"; > @@ -81,7 +83,6 @@ apb: bus@fe000000 { > #size-cells = <2>; > ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; > > - > reset: reset-controller@0 { > compatible = "amlogic,meson-a1-reset"; > reg = <0x0 0x0 0x0 0x8c>; > @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 { > clock-names = "xtal", "pclk", "baud"; > status = "disabled"; > }; > + > + clkc_periphs: periphs-clock-controller@800 { device name should be generic so clkc_periphs: clock-controller@800 would be better > + compatible = "amlogic,a1-periphs-clkc"; > + reg = <0 0x800 0 0x104>; > + #clock-cells = <1>; > + clocks = <&clkc_pll CLKID_FCLK_DIV2>, > + <&clkc_pll CLKID_FCLK_DIV3>, > + <&clkc_pll CLKID_FCLK_DIV5>, > + <&clkc_pll CLKID_FCLK_DIV7>, > + <&clkc_pll CLKID_HIFI_PLL>, > + <&xtal>; > + clock-names = "fclk_div2", "fclk_div3", > + "fclk_div5", "fclk_div7", > + "hifi_pll", "xtal"; > + }; > + > + clkc_pll: pll-clock-controller@7c80 { Same here > + compatible = "amlogic,a1-pll-clkc"; > + reg = <0 0x7c80 0 0x18c>; > + #clock-cells = <1>; > + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>, > + <&clkc_periphs CLKID_XTAL_HIFIPLL>; > + clock-names = "xtal_fixpll", "xtal_hifipll"; > + }; > }; > > gic: interrupt-controller@ff901000 {