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From: Jerome Brunet <jbrunet@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>,
	Xianwei Zhao <xianwei.zhao@amlogic.com>,
	devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Chuan Liu <chuan.liu@amlogic.com>
Subject: Re: [PATCH V2 4/4] clk: meson: c3: add c3 clock peripherals controller driver
Date: Fri, 13 Oct 2023 09:38:14 +0200	[thread overview]
Message-ID: <1jmswnvub2.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <5e0bd4bba88701dd1a7a3e89d18412f0.sboyd@kernel.org>


On Thu 12 Oct 2023 at 16:51, Stephen Boyd <sboyd@kernel.org> wrote:

> Quoting Xianwei Zhao (2023-10-09 23:29:17)
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 76be4bbd2afb..c8d59d28c8ff 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -140,6 +140,19 @@ config COMMON_CLK_C3_PLL
>>           Say Y if you want the board to work, because PLLs are the parent of most
>>           peripherals.
>>  
>> +config COMMON_CLK_C3_PERIPHERALS
>> +       tristate "Amlogic C3 peripherals clock controller"
>> +       default y
>
> Why are these default y? They should depend on something like ARM64 and
> even then I don't see why we want to enable them by default if we're
> building the ARM64 kernel.

Should indeed depend on ARM64.

Those are the main clock controllers. Like for other AML SoC families,
they are necessary to boot the device which is why they use 'default y'

Is it a problem ?

The whole meson directory depends on ARCH_MESON, so the drivers will go
away if Amlogic support is removed on ARM64.

  reply	other threads:[~2023-10-13  7:46 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10  6:29 [PATCH V2 0/4] Add C3 SoC PLLs and Peripheral clock Xianwei Zhao
2023-10-10  6:29 ` [PATCH V2 1/4] dt-bindings: clock: add Amlogic C3 PLL clock controller bindings Xianwei Zhao
2023-10-10  7:22   ` Rob Herring
2023-10-10 13:21   ` Rob Herring
2023-10-11  2:50     ` Xianwei Zhao
2023-10-13  7:35       ` Jerome Brunet
2023-10-16  6:41         ` Xianwei Zhao
2023-10-10  6:29 ` [PATCH V2 2/4] dt-bindings: clock: add Amlogic C3 peripherals " Xianwei Zhao
2023-10-10  7:22   ` Rob Herring
2023-10-10 13:25   ` Rob Herring
2023-10-11  2:54     ` Xianwei Zhao
2023-10-10  6:29 ` [PATCH V2 3/4] clk: meson: c3: add support for the C3 SoC PLL clock Xianwei Zhao
2023-10-13  7:49   ` Jerome Brunet
2023-10-17  6:15     ` Xianwei Zhao
2023-10-17 13:06       ` Jerome Brunet
2023-10-17 14:39         ` Chuan Liu
2023-10-17 14:42           ` Jerome Brunet
2023-10-10  6:29 ` [PATCH V2 4/4] clk: meson: c3: add c3 clock peripherals controller driver Xianwei Zhao
2023-10-12 23:51   ` Stephen Boyd
2023-10-13  7:38     ` Jerome Brunet [this message]
2023-10-13 22:01       ` Stephen Boyd
2023-10-16  6:49         ` Xianwei Zhao
2023-10-13  8:46   ` Jerome Brunet
     [not found]     ` <376968a3-a0f0-3045-96fe-881c2e36be7e@amlogic.com>
     [not found]       ` <1jbkcxv02x.fsf@starbuckisacylon.baylibre.com>
     [not found]         ` <ce3b4fa4-5823-4784-b41f-397ad07df3c6@amlogic.com>
2023-10-17 15:21           ` Jerome Brunet

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