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AJvYcCUzQWMH6YxZz8fwn6znxL0wyHbzRB4liHG8i/NRr3RLeMDQoDk/c+3DgXKihoYMs4QcZJYv/kldc3U=@vger.kernel.org X-Gm-Message-State: AOJu0YyItaQuMbRavC5dMb1lhimBi51eiTjx6ansZlFHGYnQuq6yIRAD HhBfgD4ugZ3Tnnh5mD+GCVoAZWPxJ+0rSb+5hwTYpE1Qq5ONNfkS38ElDRPZIeY= X-Google-Smtp-Source: AGHT+IGlyWHVSEWro5k26v/9BbprNSe8PT6hvmfZpe/tLbwFZ0rhCf+beAnjTByheeKXnnumuvMrBw== X-Received: by 2002:adf:e747:0:b0:374:c847:866 with SMTP id ffacd0b85a97d-378895cb1ddmr1033472f8f.23.1725606263243; Fri, 06 Sep 2024 00:04:23 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:4e33:801c:cee0:ee57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ca05c70d6sm10465345e9.5.2024.09.06.00.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 00:04:12 -0700 (PDT) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , chuan.liu@amlogic.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/4] clk: meson: Fix an issue with inaccurate hifi_pll frequency In-Reply-To: <20240906-fix_clk-v1-0-2977ef0d72e7@amlogic.com> (Chuan Liu via's message of "Fri, 06 Sep 2024 13:52:32 +0800") References: <20240906-fix_clk-v1-0-2977ef0d72e7@amlogic.com> Date: Fri, 06 Sep 2024 09:04:01 +0200 Message-ID: <1jo751qn4u.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri 06 Sep 2024 at 13:52, Chuan Liu via B4 Relay wrote: > Some PLLs with fractional multipliers have fractional denominators that > are fixed to "100000" instead of the previous "(1 << pll->frac.width)". > > The hifi_pll for both C3 and S4 supports a fractional multiplier and has > a fixed fractional denominator of "100000". > > Here are the results of the C3-based command tests (already defined > CLOCK_ALLOW_WRITE_DEBUGFS): > * echo 491520000 > /sys/kernel/debug/clk/hifi_pll/clk_rate > * cat /sys/kernel/debug/clk/hifi_pll/clk_rate > 491520000 > * echo 1 > /sys/kernel/debug/clk/hifi_pll/clk_prepare_enable > * cat /sys/kernel/debug/meson-clk-msr/clks/hifi_pll_clk > 491515625 +/-15625Hz > * devmem 0xfe008100 32 > 0xD00304A3 > * devmem 0xfe008104 32 > 0x00014820 > > Based on the register information read above, it can be obtained: > m = 0xA3 = 0d163; > n = 0x1 = 0d1 > frac = 0x14820 = 0d84000 > od = 0x3 = 0d3 > > hifi_pll calculates the output frequency: > calc_rate = xtal_rate / n * (m + (frac / frac_max)) >> od; > calc_rate = 24000000 / 1 * (163 + (84000 / 100000)) >> 3; > calc_rate = 491520000 > > clk_rate, msr_rate, and calc_rate all match. Thanks for the detailed description. Is there a possibility this applies to the g12/sm1 as well ? HiFi PLL has had trouble on these SoCs since support has been added. It sometimes takes a long time to report a lock. So long we consider it a failure. There was no such issue on AXG. If you check DT, it is the reason why AXG use the HiFi PLL for the sound card and G12/SM1 does not. > > The test and calculation results of S4 are consistent with those of C3, > which will not be repeated here. > > Signed-off-by: Chuan Liu > --- > Chuan Liu (4): > clk: meson: Support PLL with fixed fractional denominators > clk: meson: c3: pll: hifi_pll frequency is not accurate > clk: meson: s4: pll: hifi_pll support fractional multiplier > clk: meson: s4: pll: hifi_pll frequency is not accurate > > drivers/clk/meson/c3-pll.c | 1 + > drivers/clk/meson/clk-pll.c | 22 +++++++++++++++++++--- > drivers/clk/meson/clk-pll.h | 1 + > drivers/clk/meson/s4-pll.c | 9 +++++++-- > 4 files changed, 28 insertions(+), 5 deletions(-) > --- > base-commit: adac147c6a32e2919cb04555387e12e738991a19 > change-id: 20240904-fix_clk-668f7a1a2b16 > > Best regards, -- Jerome