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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a35607bsm7104435f8f.16.2026.09.25.07.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 07:43:47 -0700 (PDT) From: Jerome Brunet To: Cody Kang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yao Zi , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Guodong Xu Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang Subject: Re: [PATCH v2 06/17] clk: spacemit: k3: parent eDP/DP pixel clock to the PHY PLL In-Reply-To: <20260809-k3-display-v2-6-327d7910bf71@gmail.com> References: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> <20260809-k3-display-v2-6-327d7910bf71@gmail.com> Date: Fri, 25 Sep 2026 16:43:46 +0200 Message-ID: <1jwls975nh.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On dim. 09 ao=C3=BBt 2026 at 21:14, Cody Kang wrote: > The APMU eDP/DP pixel-clock muxes were parented to a placeholder, because > their real parents (the DP PHY PLLs) did not exist as clocks yet. They do > now, so point each mux at its PLL and let the pixel clock reach the > controller through the clock framework. > > Signed-off-by: Cody Kang > > --- > v2: > - no change > --- > drivers/clk/spacemit/ccu-k3.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c > index cb0c4277f72a8..afbbbd797826d 100644 > --- a/drivers/clk/spacemit/ccu-k3.c > +++ b/drivers/clk/spacemit/ccu-k3.c > @@ -937,13 +937,13 @@ CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_paren= ts, APMU_UFS_CLK_RES_CTRL, 5, >=20=20 > static const struct clk_parent_data edp0_pclk_parents[] =3D { > CCU_PARENT_HW(lcd_pxclk), > - CCU_PARENT_NAME(external_clk), > + CCU_PARENT_NAME(edp0_pll_pxclk), hidden behind this macro is a .fw_name. Basically these are your DT input names. You can't change them at will like that because your bindings are supposed to be stable. You should not use placeholder name, ever. No need to make the name too specific either, from the beginning it should have been something like "pixel_pll" or whatever your doc refer it with. "external_clk" is not declared in your bindings AFAICT, so at least it should be fine to remove it. There need to be a dt-binding patch documenting the new name you need and then you can start using it in the driver. In the future, please try to document all the inputs of your controller in the bindings. Even if you do not use them yet, they exist. > }; > CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2,= 1, BIT(1), 0); >=20=20 > static const struct clk_parent_data edp1_pclk_parents[] =3D { > CCU_PARENT_HW(dsi4ln2_lcd_pxclk), > - CCU_PARENT_NAME(external_clk), > + CCU_PARENT_NAME(edp1_pll_pxclk), > }; > CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18= , 1, BIT(17), 0); >=20=20 > > --=20 > 2.43.0 > --=20 Jerome