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Fri, 04 Aug 2023 03:07:05 -0700 (PDT) Received: from localhost ([2a01:e0a:3c5:5fb1:aeaf:609a:5eef:39a8]) by smtp.gmail.com with ESMTPSA id d10-20020adffd8a000000b003143ba62cf4sm2087969wrr.86.2023.08.04.03.07.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 03:07:05 -0700 (PDT) References: <20230803-amlogic-v6-4-upstream-dsi-ccf-vim3-v7-0-762219fc5b28@linaro.org> <20230803-amlogic-v6-4-upstream-dsi-ccf-vim3-v7-4-762219fc5b28@linaro.org> User-agent: mu4e 1.8.13; emacs 28.2 From: Jerome Brunet To: Neil Armstrong , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Martin Blumenstingl , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v7 4/9] clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF Date: Fri, 04 Aug 2023 12:04:34 +0200 In-reply-to: <20230803-amlogic-v6-4-upstream-dsi-ccf-vim3-v7-4-762219fc5b28@linaro.org> Message-ID: <1jwmybnmt3.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Thu 03 Aug 2023 at 14:03, Neil Armstrong wrote: > In order to setup the DSI clock, let's make the unused VCLK2 clock path > configuration via CCF. > > The nocache option is removed from following clocks: > - vclk2_sel > - vclk2_input > - vclk2_div > - vclk2 > - vclk_div1 > - vclk2_div2_en > - vclk2_div4_en > - vclk2_div6_en > - vclk2_div12_en > - vclk2_div2 > - vclk2_div4 > - vclk2_div6 > - vclk2_div12 > - cts_encl_sel > > vclk2 and vclk2_div uses the newly introduced vclk regmap driver > to handle the enable and reset bits. > > In order to set a rate on cts_encl via the vclk2 clock path, > the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order > to keep CCF from selection a parent. > The parents of cts_encl_sel & vclk2_sel are expected to be defined > in DT. > > The following clock scheme is to be used for DSI: > > xtal > \_ gp0_pll_dco > \_ gp0_pll > |- vclk2_sel > | \_ vclk2_input > | \_ vclk2_div > | \_ vclk2 > | \_ vclk2_div1 > | \_ cts_encl_sel > | \_ cts_encl -> to VPU LCD Encoder > |- mipi_dsi_pxclk_sel > \_ mipi_dsi_pxclk_div > \_ mipi_dsi_pxclk -> to DSI controller > > The mipi_dsi_pxclk_div is set as RO in order to use the same GP0 > for mipi_dsi_pxclk and vclk2_input. > > Signed-off-by: Neil Armstrong > --- > drivers/clk/meson/g12a.c | 43 ++++++++++++++++++++++++++----------------- > 1 file changed, 26 insertions(+), 17 deletions(-) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index 5d62134335c1..552c8efb1ad8 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -22,6 +22,7 @@ > #include "clk-regmap.h" > #include "clk-cpu-dyndiv.h" > #include "vid-pll-div.h" > +#include "vclk.h" > #include "meson-eeclk.h" > #include "g12a.h" > > @@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = g12a_vclk_parent_hws, > .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws), > - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > }; > > @@ -3193,7 +3194,7 @@ static struct clk_regmap g12a_vclk2_input = { > .ops = &clk_regmap_gate_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT, ... oh, I see. Ignore the comment patch #2 > }, > }; > > @@ -3215,19 +3216,22 @@ static struct clk_regmap g12a_vclk_div = { > }; > > static struct clk_regmap g12a_vclk2_div = { > - .data = &(struct clk_regmap_div_data){ > + .data = &(struct clk_regmap_vclk_div_data){ > .offset = HHI_VIID_CLK_DIV, > .shift = 0, > .width = 8, > + .enable_bit_idx = 16, > + .reset_bit_idx = 17, > + .flags = CLK_DIVIDER_ROUND_CLOSEST, > }, > .hw.init = &(struct clk_init_data){ > .name = "vclk2_div", > - .ops = &clk_regmap_divider_ops, > + .ops = &clk_regmap_vclk_div_ops, > .parent_hws = (const struct clk_hw *[]) { > &g12a_vclk2_input.hw > }, > .num_parents = 1, > - .flags = CLK_GET_RATE_NOCACHE, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, > }, > }; > > @@ -3246,16 +3250,17 @@ static struct clk_regmap g12a_vclk = { > }; > > static struct clk_regmap g12a_vclk2 = { > - .data = &(struct clk_regmap_gate_data){ > + .data = &(struct clk_regmap_vclk_data){ > .offset = HHI_VIID_CLK_CNTL, > - .bit_idx = 19, > + .enable_bit_idx = 19, > + .reset_bit_idx = 15, > }, > .hw.init = &(struct clk_init_data) { > .name = "vclk2", > - .ops = &clk_regmap_gate_ops, > + .ops = &clk_regmap_vclk_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, > }, > }; > > @@ -3339,7 +3344,7 @@ static struct clk_regmap g12a_vclk2_div1 = { > .ops = &clk_regmap_gate_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3353,7 +3358,7 @@ static struct clk_regmap g12a_vclk2_div2_en = { > .ops = &clk_regmap_gate_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3367,7 +3372,7 @@ static struct clk_regmap g12a_vclk2_div4_en = { > .ops = &clk_regmap_gate_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3381,7 +3386,7 @@ static struct clk_regmap g12a_vclk2_div6_en = { > .ops = &clk_regmap_gate_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3395,7 +3400,7 @@ static struct clk_regmap g12a_vclk2_div12_en = { > .ops = &clk_regmap_gate_ops, > .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, > .num_parents = 1, > - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3461,6 +3466,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = { > &g12a_vclk2_div2_en.hw > }, > .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3474,6 +3480,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = { > &g12a_vclk2_div4_en.hw > }, > .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3487,6 +3494,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = { > &g12a_vclk2_div6_en.hw > }, > .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3500,6 +3508,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = { > &g12a_vclk2_div12_en.hw > }, > .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > }, > }; > > @@ -3561,7 +3570,7 @@ static struct clk_regmap g12a_cts_encl_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = g12a_cts_parent_hws, > .num_parents = ARRAY_SIZE(g12a_cts_parent_hws), > - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > }; > > @@ -3717,7 +3726,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = { > .ops = &clk_regmap_mux_ops, > .parent_hws = g12a_mipi_dsi_pxclk_parent_hws, > .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws), > - .flags = CLK_SET_RATE_NO_REPARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > }; > > @@ -3729,7 +3738,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_div = { > }, > .hw.init = &(struct clk_init_data){ > .name = "mipi_dsi_pxclk_div", > - .ops = &clk_regmap_divider_ops, > + .ops = &clk_regmap_divider_ro_ops, > .parent_hws = (const struct clk_hw *[]) { > &g12a_mipi_dsi_pxclk_sel.hw > },