Re: [PATCH v3 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings

Rob Herring (Arm)
2024-05-20T19:02:46Z

On Wed, 15 May 2024 21:47:25 +0300, Dmitry Rokosov wrote:
> The 'syspll' PLL is a general-purpose PLL designed specifically for the
> CPU clock. It is capable of producing output frequencies within the
> range of 768MHz to 1536MHz.
>
> The 'syspll_in' source clock is an optional parent connection from the
> peripherals clock controller.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
> ---
> .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 9 +++++++--
> include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
>

Acked-by: Rob Herring (Arm) <robh@kernel.org>