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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f85c2sm16339601f8f.91.2025.02.18.11.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 11:34:28 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 08/15] clk: sunxi-ng: a523: add system mod clocks Date: Tue, 18 Feb 2025 20:34:27 +0100 Message-ID: <2013031.usQuhbGJ8B@jernej-laptop> In-Reply-To: <20250214125359.5204-9-andre.przywara@arm.com> References: <20250214125359.5204-1-andre.przywara@arm.com> <20250214125359.5204-9-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne petek, 14. februar 2025 ob 13:53:52 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > Add the clocks driving some core system related subsystems of the SoC: > the "CE" crypto engine, the high speed timers, the DRAM and the associated > MBUS clock, and the PCIe clock. >=20 > Signed-off-by: Andre Przywara > --- > drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 119 +++++++++++++++++++++++++ > 1 file changed, 119 insertions(+) >=20 > diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-n= g/ccu-sun55i-a523.c > index 0ef1fd71a1ca5..b68c44bce825f 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c > +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c > @@ -423,6 +423,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", = gpu_parents, 0x670, > BIT(31), /* gate */ > 0); > =20 > +static const struct clk_parent_data ce_parents[] =3D { > + { .fw_name =3D "hosc" }, > + { .hw =3D &pll_periph0_480M_clk.common.hw }, > + { .hw =3D &pll_periph0_400M_clk.hw }, > + { .hw =3D &pll_periph0_300M_clk.hw }, > +}; > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); > + > static const struct clk_hw *ve_parents[] =3D { > &pll_ve_clk.common.hw, > &pll_periph0_480M_clk.common.hw, > @@ -435,6 +447,65 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve= _parents, 0x690, > BIT(31), /* gate */ > CLK_SET_RATE_PARENT); > =20 > +static const struct clk_parent_data hstimer_parents[] =3D { > + { .fw_name =3D "hosc" }, > + { .fw_name =3D "iosc" }, > + { .fw_name =3D "losc" }, > + { .hw =3D &pll_periph0_200M_clk.hw }, > +}; > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0", > + hstimer_parents, 0x730, > + 0, 0, /* M */ > + 0, 3, /* P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); CLK_SET_RATE_PARENT doesn't make much sense for fixed clocks. > + > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1", > + hstimer_parents, > + 0x734, > + 0, 0, /* M */ > + 0, 3, /* P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2", > + hstimer_parents, > + 0x738, > + 0, 0, /* M */ > + 0, 3, /* P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3", > + hstimer_parents, > + 0x73c, > + 0, 0, /* M */ > + 0, 3, /* P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4", > + hstimer_parents, > + 0x740, > + 0, 0, /* M */ > + 0, 3, /* P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5", > + hstimer_parents, > + 0x744, > + 0, 0, /* M */ > + 0, 3, /* P */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > static const struct clk_parent_data iommu_parents[] =3D { > { .hw =3D &pll_periph0_600M_clk.hw }, > { .hw =3D &pll_ddr0_clk.common.hw }, > @@ -450,6 +521,34 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(iommu_clk, "io= mmu", iommu_parents, 0x7b0, > BIT(31), /* gate */ > CLK_SET_RATE_PARENT); > =20 > +static const struct clk_hw *dram_parents[] =3D { > + &pll_ddr0_clk.common.hw, > + &pll_periph0_600M_clk.hw, > + &pll_periph0_480M_clk.common.hw, > + &pll_periph0_400M_clk.hw, > + &pll_periph0_150M_clk.hw, > +}; > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x80= 0, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_IS_CRITICAL); Same comment as for IOMMU clock. Update bit is needed to actually apply con= figuration. Best regards, Jernej > + > +static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus", > + &dram_clk.common.hw, 4, 1, 0); > + > +static const struct clk_parent_data losc_hosc_parents[] =3D { > + { .fw_name =3D "hosc" }, > + { .fw_name =3D "losc" }, > +}; > + > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", > + losc_hosc_parents, 0xaa0, > + 0, 5, /* M */ > + 24, 1, /* mux */ > + BIT(31), /* gate */ > + 0); > + > static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(= 31), 0); > =20 > /* TODO: add mux between 32kOSC and PERIPH0/18750 */ > @@ -584,8 +683,17 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D= { > &di_clk.common, > &g2d_clk.common, > &gpu_clk.common, > + &ce_clk.common, > &ve_clk.common, > + &hstimer0_clk.common, > + &hstimer1_clk.common, > + &hstimer2_clk.common, > + &hstimer3_clk.common, > + &hstimer4_clk.common, > + &hstimer5_clk.common, > &iommu_clk.common, > + &dram_clk.common, > + &pcie_aux_clk.common, > &hdmi_24M_clk.common, > &hdmi_cec_32k_clk.common, > &hdmi_cec_clk.common, > @@ -644,11 +752,22 @@ static struct clk_hw_onecell_data sun55i_a523_hw_cl= ks =3D { > [CLK_AHB] =3D &ahb_clk.common.hw, > [CLK_APB0] =3D &apb0_clk.common.hw, > [CLK_APB1] =3D &apb1_clk.common.hw, > + [CLK_MBUS] =3D &mbus_clk.hw, > [CLK_DE] =3D &de_clk.common.hw, > [CLK_DI] =3D &di_clk.common.hw, > [CLK_G2D] =3D &g2d_clk.common.hw, > [CLK_GPU] =3D &gpu_clk.common.hw, > + [CLK_CE] =3D &ce_clk.common.hw, > [CLK_VE] =3D &ve_clk.common.hw, > + [CLK_HSTIMER0] =3D &hstimer0_clk.common.hw, > + [CLK_HSTIMER1] =3D &hstimer1_clk.common.hw, > + [CLK_HSTIMER2] =3D &hstimer2_clk.common.hw, > + [CLK_HSTIMER3] =3D &hstimer3_clk.common.hw, > + [CLK_HSTIMER4] =3D &hstimer4_clk.common.hw, > + [CLK_HSTIMER5] =3D &hstimer5_clk.common.hw, > + [CLK_IOMMU] =3D &iommu_clk.common.hw, > + [CLK_DRAM] =3D &dram_clk.common.hw, > + [CLK_PCIE_AUX] =3D &pcie_aux_clk.common.hw, > [CLK_HDMI_24M] =3D &hdmi_24M_clk.common.hw, > [CLK_HDMI_CEC_32K] =3D &hdmi_cec_32k_clk.common.hw, > [CLK_HDMI_CEC] =3D &hdmi_cec_clk.common.hw, >=20