From: Stephen Boyd <sboyd@codeaurora.org>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: heiko@sntech.de, linux-rockchip@lists.infradead.org,
Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 4/9] clk: rockchip: add new clock type and controller for rk3036
Date: Tue, 22 Sep 2015 15:41:25 -0700 [thread overview]
Message-ID: <20150922224125.GK23081@codeaurora.org> (raw)
In-Reply-To: <1442478540-15068-5-git-send-email-zhengxing@rock-chips.com>
On 09/17, Xing Zheng wrote:
> +
> +static void rockchip_rk3036_pll_init(struct clk_hw *hw)
init ops are "discouraged". Could we do this through assigned
rates instead?
> +{
> + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
> + const struct rockchip_pll_rate_table *rate;
> + unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac;
> + unsigned long drate;
> + u32 pllcon;
> +
> + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
> + return;
I don't understand what this one does though. This check isn't in
the set rate ops.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-09-22 22:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-17 8:28 [PATCH v2 0/9] Build and support rk3036 SoC platform Xing Zheng
2015-09-17 8:28 ` [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036 Xing Zheng
2015-09-17 9:47 ` Heiko Stübner
2015-09-24 3:04 ` Xing Zheng
2015-09-24 3:31 ` Xing Zheng
2015-10-07 10:24 ` Heiko Stuebner
2015-09-17 8:28 ` [PATCH v2 4/9] clk: rockchip: add new clock type and " Xing Zheng
2015-09-17 9:54 ` Heiko Stübner
2015-09-22 22:41 ` Stephen Boyd [this message]
2015-09-22 22:58 ` Heiko Stübner
2015-09-22 23:19 ` Stephen Boyd
2015-09-30 23:32 ` Heiko Stübner
2015-10-01 0:51 ` Stephen Boyd
2015-09-17 9:59 ` [PATCH v2 0/9] Build and support rk3036 SoC platform Heiko Stübner
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