From: Shawn Guo <shawnguo@kernel.org>
To: Shengjiu Wang <shengjiu.wang@freescale.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
linux@arm.linux.org.uk, pawel.moll@arm.com,
ijc+devicetree@hellion.org.uk, mturquette@baylibre.com,
sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, kernel@pengutronix.de, galak@codeaurora.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree
Date: Sat, 10 Oct 2015 09:11:55 +0800 [thread overview]
Message-ID: <20151010011155.GH22673@tiger> (raw)
In-Reply-To: <20151009091528.GA25804@shlinux2>
On Fri, Oct 09, 2015 at 05:15:30PM +0800, Shengjiu Wang wrote:
> SPDIF_GCLK is also spdif's clock, it use a same enable bit with SPDIF_ROOT_CLK,
> We didn't separate them in clock tree before.
Is it the clock described as "Global clock" in Reference Manual, SPDIF
chapter? If that's the case, you are just adding a missing SPDIF clock
rather than fixing a low power mode issue, and I will be fine. But
still you should reword the commit log to make it clear, that the patch
is to correct a SPDIF clock setting issue, which is just discovered by
low power mode support.
Shawn
next prev parent reply other threads:[~2015-10-10 1:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-15 10:01 [PATCH V2 0/2] fix clock issue for fsl,spdi Shengjiu Wang
2015-09-15 10:01 ` [PATCH V2 1/2] clk: imx6: Add SPDIF_GCLK clock in clock tree Shengjiu Wang
2015-09-23 15:33 ` Shawn Guo
2015-09-24 5:43 ` Shengjiu Wang
2015-09-24 11:57 ` Shawn Guo
2015-10-09 9:15 ` Shengjiu Wang
2015-10-10 1:11 ` Shawn Guo [this message]
2015-10-10 1:45 ` Shengjiu Wang
2015-09-15 10:01 ` [PATCH V2 2/2] ARM: dts: imx6: change the core clock of spdif Shengjiu Wang
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