[PATCH 0/5] ARM: dts: add device tree support for NS, NSP, and NS2 clocks

[PATCH 0/5] ARM: dts: add device tree support for NS, NSP, and NS2 clocks

[Jon Mason]

This patch series adds device tree support for the Broadcom Northstar,
Northstar Plus, and Northstar 2 clocks.  This is being sent as a
separate patch series due to the the clk maintainer(s) not wanting to
pull in device tree changes into the clk repo.  This series is an RFC
due to a potential merge "race" between the device tree changes and the
clk changes.  If the device tree changes go in before the clk changes,
there is a window where there are non-working clk entries in the device
tree.  So, these patches will be officially pushed once the clk changes
are merged.

Thanks,
Jon

[RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding

[Jon Mason]

Document the device tree bindings for Broadcom Northstar Plus
architecture based clock controller

Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
 .../bindings/clock/brcm,iproc-clocks.txt           | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index da8d9bb..b3c3e9d 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -130,3 +130,33 @@ These clock IDs are defined in:
     ch3_unused mipipll          4       BCM_CYGNUS_MIPIPLL_CH3_UNUSED
     ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED
     ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED
+
+Northstar and Northstar Plus
+------
+PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
+ "brcm,nsp-armpll"
+ "brcm,nsp-genpll"
+ "brcm,nsp-lcpll0"
+
+The following table defines the set of PLL/clock index and ID for Northstar and
+Northstar Plus.  These clock IDs are defined in:
+    "include/dt-bindings/clock/bcm-nsp.h"
+
+    Clock	Source		Index	ID
+    ---		-----		-----	---------
+    crystal	N/A		N/A	N/A
+
+    armpll	crystal		N/A	N/A
+
+    genpll	crystal		0	BCM_NSP_GENPLL
+    phy		genpll		1	BCM_NSP_GENPLL_PHY_CLK
+    ethernetclk	genpll		2	BCM_NSP_GENPLL_ENET_SW_CLK
+    usbclk	genpll		3	BCM_NSP_GENPLL_USB_PHY_REF_CLK
+    iprocfast	genpll		4	BCM_NSP_GENPLL_IPROCFAST_CLK
+    sata1	genpll		5	BCM_NSP_GENPLL_SATA1_CLK
+    sata2	genpll		6	BCM_NSP_GENPLL_SATA2_CLK
+
+    lcpll0	crystal		0	BCM_NSP_LCPLL0
+    pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
+    sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
+    ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
-- 
1.9.1

Re: [RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding

[Ray Jui]

Shouldn't the device tree binding document go with the other patch
series since both the binding document and drivers are merged by Michael
or Stephen?

On 10/13/2015 2:22 PM, Jon Mason wrote:
> Document the device tree bindings for Broadcom Northstar Plus
> architecture based clock controller
> 
> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> ---
>  .../bindings/clock/brcm,iproc-clocks.txt           | 30 ++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> index da8d9bb..b3c3e9d 100644
> --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> @@ -130,3 +130,33 @@ These clock IDs are defined in:
>      ch3_unused mipipll          4       BCM_CYGNUS_MIPIPLL_CH3_UNUSED
>      ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED
>      ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED
> +
> +Northstar and Northstar Plus
> +------
> +PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
> + "brcm,nsp-armpll"
> + "brcm,nsp-genpll"
> + "brcm,nsp-lcpll0"

So the current clock driver also supports NS? That will be nice and that
indicates all the clock related registers/offsets are exactly the same
between NS and NSP?

> +
> +The following table defines the set of PLL/clock index and ID for Northstar and
> +Northstar Plus.  These clock IDs are defined in:
> +    "include/dt-bindings/clock/bcm-nsp.h"
> +
> +    Clock	Source		Index	ID
> +    ---		-----		-----	---------
> +    crystal	N/A		N/A	N/A
> +
> +    armpll	crystal		N/A	N/A
> +
> +    genpll	crystal		0	BCM_NSP_GENPLL
> +    phy		genpll		1	BCM_NSP_GENPLL_PHY_CLK
> +    ethernetclk	genpll		2	BCM_NSP_GENPLL_ENET_SW_CLK
> +    usbclk	genpll		3	BCM_NSP_GENPLL_USB_PHY_REF_CLK
> +    iprocfast	genpll		4	BCM_NSP_GENPLL_IPROCFAST_CLK
> +    sata1	genpll		5	BCM_NSP_GENPLL_SATA1_CLK
> +    sata2	genpll		6	BCM_NSP_GENPLL_SATA2_CLK
> +
> +    lcpll0	crystal		0	BCM_NSP_LCPLL0
> +    pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
> +    sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
> +    ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
> 

Re: [RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding

[Jon Mason]

On Tue, Oct 13, 2015 at 03:17:36PM -0700, Ray Jui wrote:
> Shouldn't the device tree binding document go with the other patch
> series since both the binding document and drivers are merged by Michael
> or Stephen?
> 
> On 10/13/2015 2:22 PM, Jon Mason wrote:
> > Document the device tree bindings for Broadcom Northstar Plus
> > architecture based clock controller
> > 
> > Signed-off-by: Jon Mason <jonmason@broadcom.com>
> > ---
> >  .../bindings/clock/brcm,iproc-clocks.txt           | 30 ++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> > index da8d9bb..b3c3e9d 100644
> > --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> > +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> > @@ -130,3 +130,33 @@ These clock IDs are defined in:
> >      ch3_unused mipipll          4       BCM_CYGNUS_MIPIPLL_CH3_UNUSED
> >      ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED
> >      ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED
> > +
> > +Northstar and Northstar Plus
> > +------
> > +PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
> > + "brcm,nsp-armpll"
> > + "brcm,nsp-genpll"
> > + "brcm,nsp-lcpll0"
> 
> So the current clock driver also supports NS? That will be nice and that
> indicates all the clock related registers/offsets are exactly the same
> between NS and NSP?

Yes.  The register offsets are different, but everything else is
identical.

> 
> > +
> > +The following table defines the set of PLL/clock index and ID for Northstar and
> > +Northstar Plus.  These clock IDs are defined in:
> > +    "include/dt-bindings/clock/bcm-nsp.h"
> > +
> > +    Clock	Source		Index	ID
> > +    ---		-----		-----	---------
> > +    crystal	N/A		N/A	N/A
> > +
> > +    armpll	crystal		N/A	N/A
> > +
> > +    genpll	crystal		0	BCM_NSP_GENPLL
> > +    phy		genpll		1	BCM_NSP_GENPLL_PHY_CLK
> > +    ethernetclk	genpll		2	BCM_NSP_GENPLL_ENET_SW_CLK
> > +    usbclk	genpll		3	BCM_NSP_GENPLL_USB_PHY_REF_CLK
> > +    iprocfast	genpll		4	BCM_NSP_GENPLL_IPROCFAST_CLK
> > +    sata1	genpll		5	BCM_NSP_GENPLL_SATA1_CLK
> > +    sata2	genpll		6	BCM_NSP_GENPLL_SATA2_CLK
> > +
> > +    lcpll0	crystal		0	BCM_NSP_LCPLL0
> > +    pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
> > +    sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
> > +    ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
> > 

[RFC 2/5] ARM: dts: enable clock support for Broadcom NSP

[Jon Mason]

Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC

Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi | 93 ++++++++++++++++++++++++++++++++----------
 1 file changed, 72 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..768ee24 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/bcm-nsp.h>
 
 #include "skeleton.dtsi"
 
@@ -42,7 +43,7 @@
 
 	mpcore {
 		compatible = "simple-bus";
-		ranges = <0x00000000 0x19020000 0x00003000>;
+		ranges = <0x00000000 0x19000000 0x00023000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
@@ -58,27 +59,34 @@
 			};
 		};
 
-		L2: l2-cache {
-			compatible = "arm,pl310-cache";
-			reg = <0x2000 0x1000>;
-			cache-unified;
-			cache-level = <2>;
+		a9pll: arm_clk@0000 {
+			#clock-cells = <0>;
+			compatible = "brcm,nsp-armpll";
+			clocks = <&osc>;
+			reg = <0x0000 0x1000>;
+		};
+
+		timer@20200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x20200 0x100>;
+			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
 		};
 
-		gic: interrupt-controller@19021000 {
+		gic: interrupt-controller@21000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
-			reg = <0x1000 0x1000>,
-			      <0x0100 0x100>;
+			reg = <0x21000 0x1000>,
+			      <0x20100 0x100>;
 		};
 
-		timer@19020200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x0200 0x100>;
-			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&periph_clk>;
+		L2: l2-cache {
+			compatible = "arm,pl310-cache";
+			reg = <0x22000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
 		};
 	};
 
@@ -87,33 +95,76 @@
 		#size-cells = <1>;
 		ranges;
 
-		periph_clk: periph_clk {
+		osc: oscillator {
+			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		iprocmed: iprocmed {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+
+		iprocslow: iprocslow {
 			#clock-cells = <0>;
-			clock-frequency = <500000000>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+
+		periph_clk: periph_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&a9pll>;
+			clock-div = <2>;
+			clock-mult = <1>;
 		};
 	};
 
 	axi {
 		compatible = "simple-bus";
-		ranges = <0x00000000 0x18000000 0x00001000>;
+		ranges = <0x00000000 0x18000000 0x0003f164>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		uart0: serial@18000300 {
+		uart0: serial@00300 {
 			compatible = "ns16550a";
-			reg = <0x0300 0x100>;
+			reg = <0x00300 0x100>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			clock-frequency = <62499840>;
 			status = "disabled";
 		};
 
-		uart1: serial@18000400 {
+		uart1: serial@00400 {
 			compatible = "ns16550a";
-			reg = <0x0400 0x100>;
+			reg = <0x00400 0x100>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			clock-frequency = <62499840>;
 			status = "disabled";
 		};
+
+		lcpll0: lcpll0@3f100 {
+			#clock-cells = <1>;
+			compatible = "brcm,nsp-lcpll0";
+			reg = <0x3f100 0x14>;
+			clocks = <&osc>;
+			clock-output-names = "lcpll0", "pcie_phy", "sdio",
+					     "ddr_phy";
+		};
+
+		genpll: genpll@3f140 {
+			#clock-cells = <1>;
+			compatible = "brcm,nsp-genpll";
+			reg = <0x3f140 0x24>;
+			clocks = <&osc>;
+			clock-output-names = "genpll", "phy", "ethernetclk",
+					     "usbclk", "iprocfast", "sata1",
+					     "sata2";
+		};
 	};
 };
-- 
1.9.1

[RFC 3/5] ARM: dts: enable clock support for BCM5301X

[Jon Mason]

Replace current device tree dummy clocks with real clock support for
Broadcom Northstar SoCs.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
 arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++---------
 1 file changed, 69 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 6f50f67..1eca551 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,7 @@
  * Licensed under the GNU/GPL. See COPYING for details.
  */
 
+#include <dt-bindings/clock/bcm-nsp.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -42,41 +43,48 @@
 
 	mpcore {
 		compatible = "simple-bus";
-		ranges = <0x00000000 0x19020000 0x00003000>;
+		ranges = <0x00000000 0x19000000 0x00023000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		scu@0000 {
+		a9pll: arm_clk@00000 {
+			#clock-cells = <0>;
+			compatible = "brcm,nsp-armpll";
+			clocks = <&osc>;
+			reg = <0x00000 0x1000>;
+		};
+
+		scu@20000 {
 			compatible = "arm,cortex-a9-scu";
-			reg = <0x0000 0x100>;
+			reg = <0x20000 0x100>;
 		};
 
-		timer@0200 {
+		timer@20200 {
 			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x0200 0x100>;
+			reg = <0x20200 0x100>;
 			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_periph>;
+			clocks = <&periph_clk>;
 		};
 
-		local-timer@0600 {
+		local-timer@20600 {
 			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x0600 0x100>;
+			reg = <0x20600 0x100>;
 			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_periph>;
+			clocks = <&periph_clk>;
 		};
 
-		gic: interrupt-controller@1000 {
+		gic: interrupt-controller@21000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
-			reg = <0x1000 0x1000>,
-			      <0x0100 0x100>;
+			reg = <0x21000 0x1000>,
+			      <0x20100 0x100>;
 		};
 
-		L2: cache-controller@2000 {
+		L2: cache-controller@22000 {
 			compatible = "arm,pl310-cache";
-			reg = <0x2000 0x1000>;
+			reg = <0x22000 0x1000>;
 			cache-unified;
 			arm,shared-override;
 			prefetch-data = <1>;
@@ -94,14 +102,37 @@
 
 	clocks {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
+		ranges;
 
-		/* As long as we do not have a real clock driver us this
-		 * fixed clock */
-		clk_periph: periph {
+		osc: oscillator {
+			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		iprocmed: iprocmed {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+
+		iprocslow: iprocslow {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+
+		periph_clk: periph_clk {
 			#clock-cells = <0>;
-			clock-frequency = <400000000>;
+			compatible = "fixed-factor-clock";
+			clocks = <&a9pll>;
+			clock-div = <2>;
+			clock-mult = <1>;
 		};
 	};
 
@@ -178,6 +209,25 @@
 		};
 	};
 
+	lcpll0: lcpll0@1800c100 {
+		#clock-cells = <1>;
+		compatible = "brcm,nsp-lcpll0";
+		reg = <0x1800c100 0x14>;
+		clocks = <&osc>;
+		clock-output-names = "lcpll0", "pcie_phy", "sdio",
+				     "ddr_phy";
+	};
+
+	genpll: genpll@1800c140 {
+		#clock-cells = <1>;
+		compatible = "brcm,nsp-genpll";
+		reg = <0x1800c140 0x24>;
+		clocks = <&osc>;
+		clock-output-names = "genpll", "phy", "ethernetclk",
+				     "usbclk", "iprocfast", "sata1",
+				     "sata2";
+	};
+
 	nand: nand@18028000 {
 		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
-- 
1.9.1

Re: [RFC 3/5] ARM: dts: enable clock support for BCM5301X

[Hauke Mehrtens]

On 10/13/2015 11:22 PM, Jon Mason wrote:
> Replace current device tree dummy clocks with real clock support for
> Broadcom Northstar SoCs.
> 
> Signed-off-by: Jon Mason <jonmason@broadcom.com>

The clock-frequency of the uarts should also be replaced with the
correct clock from the clock driver.

Hauke
> ---
>  arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++---------
>  1 file changed, 69 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
> index 6f50f67..1eca551 100644
> --- a/arch/arm/boot/dts/bcm5301x.dtsi
> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
> @@ -8,6 +8,7 @@
>   * Licensed under the GNU/GPL. See COPYING for details.
>   */
>  
> +#include <dt-bindings/clock/bcm-nsp.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> @@ -42,41 +43,48 @@
>  
>  	mpcore {
>  		compatible = "simple-bus";
> -		ranges = <0x00000000 0x19020000 0x00003000>;
> +		ranges = <0x00000000 0x19000000 0x00023000>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  
> -		scu@0000 {
> +		a9pll: arm_clk@00000 {
> +			#clock-cells = <0>;
> +			compatible = "brcm,nsp-armpll";
> +			clocks = <&osc>;
> +			reg = <0x00000 0x1000>;
> +		};
> +
> +		scu@20000 {
>  			compatible = "arm,cortex-a9-scu";
> -			reg = <0x0000 0x100>;
> +			reg = <0x20000 0x100>;
>  		};
>  
> -		timer@0200 {
> +		timer@20200 {
>  			compatible = "arm,cortex-a9-global-timer";
> -			reg = <0x0200 0x100>;
> +			reg = <0x20200 0x100>;
>  			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk_periph>;
> +			clocks = <&periph_clk>;
>  		};
>  
> -		local-timer@0600 {
> +		local-timer@20600 {
>  			compatible = "arm,cortex-a9-twd-timer";
> -			reg = <0x0600 0x100>;
> +			reg = <0x20600 0x100>;
>  			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clk_periph>;
> +			clocks = <&periph_clk>;
>  		};
>  
> -		gic: interrupt-controller@1000 {
> +		gic: interrupt-controller@21000 {
>  			compatible = "arm,cortex-a9-gic";
>  			#interrupt-cells = <3>;
>  			#address-cells = <0>;
>  			interrupt-controller;
> -			reg = <0x1000 0x1000>,
> -			      <0x0100 0x100>;
> +			reg = <0x21000 0x1000>,
> +			      <0x20100 0x100>;
>  		};
>  
> -		L2: cache-controller@2000 {
> +		L2: cache-controller@22000 {
>  			compatible = "arm,pl310-cache";
> -			reg = <0x2000 0x1000>;
> +			reg = <0x22000 0x1000>;
>  			cache-unified;
>  			arm,shared-override;
>  			prefetch-data = <1>;
> @@ -94,14 +102,37 @@
>  
>  	clocks {
>  		#address-cells = <1>;
> -		#size-cells = <0>;
> +		#size-cells = <1>;
> +		ranges;
>  
> -		/* As long as we do not have a real clock driver us this
> -		 * fixed clock */
> -		clk_periph: periph {
> +		osc: oscillator {
> +			#clock-cells = <0>;
>  			compatible = "fixed-clock";
> +			clock-frequency = <25000000>;
> +		};
> +
> +		iprocmed: iprocmed {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +		};
> +
> +		iprocslow: iprocslow {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
> +			clock-div = <4>;
> +			clock-mult = <1>;
> +		};
> +
> +		periph_clk: periph_clk {
>  			#clock-cells = <0>;
> -			clock-frequency = <400000000>;
> +			compatible = "fixed-factor-clock";
> +			clocks = <&a9pll>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
>  		};
>  	};
>  
> @@ -178,6 +209,25 @@
>  		};
>  	};
>  
> +	lcpll0: lcpll0@1800c100 {
> +		#clock-cells = <1>;
> +		compatible = "brcm,nsp-lcpll0";
> +		reg = <0x1800c100 0x14>;
> +		clocks = <&osc>;
> +		clock-output-names = "lcpll0", "pcie_phy", "sdio",
> +				     "ddr_phy";
> +	};
> +
> +	genpll: genpll@1800c140 {
> +		#clock-cells = <1>;
> +		compatible = "brcm,nsp-genpll";
> +		reg = <0x1800c140 0x24>;
> +		clocks = <&osc>;
> +		clock-output-names = "genpll", "phy", "ethernetclk",
> +				     "usbclk", "iprocfast", "sata1",
> +				     "sata2";
> +	};
> +
>  	nand: nand@18028000 {
>  		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
>  		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
> 

[RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding

[Jon Mason]

Document the device tree bindings for Broadcom Northstar 2 architecture
based clock controller

Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
 .../bindings/clock/brcm,iproc-clocks.txt           | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index b3c3e9d..ede65a5 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -160,3 +160,51 @@ Northstar Plus.  These clock IDs are defined in:
     pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
     sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
     ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
+
+Northstar 2
+-----------
+PLL and leaf clock compatible strings for Northstar 2 are:
+    "brcm,ns2-genpll-scr"
+    "brcm,ns2-genpll-sw"
+    "brcm,ns2-lcpll-ddr"
+    "brcm,ns2-lcpll-ports"
+
+The following table defines the set of PLL/clock index and ID for Northstar 2.
+These clock IDs are defined in:
+    "include/dt-bindings/clock/bcm-ns2.h"
+
+    Clock	Source		Index	ID
+    ---		-----		-----	---------
+    crystal	N/A		N/A	N/A
+
+    genpll_scr	crystal		0	BCM_NS2_GENPLL_SCR
+    scr		genpll_scr	1	BCM_NS2_GENPLL_SCR_SCR_CLK
+    fs		genpll_scr	2	BCM_NS2_GENPLL_SCR_FS_CLK
+    audio_ref	genpll_scr	3	BCM_NS2_GENPLL_SCR_AUDIO_CLK
+    ch3_unused	genpll_scr	4	BCM_NS2_GENPLL_SCR_CH3_UNUSED
+    ch4_unused	genpll_scr	5	BCM_NS2_GENPLL_SCR_CH4_UNUSED
+    ch5_unused	genpll_scr	6	BCM_NS2_GENPLL_SCR_CH5_UNUSED
+
+    genpll_sw	crystal		0	BCM_NS2_GENPLL_SW
+    rpe		genpll_sw	1	BCM_NS2_GENPLL_SW_RPE_CLK
+    250		genpll_sw	2	BCM_NS2_GENPLL_SW_250_CLK
+    nic		genpll_sw	3	BCM_NS2_GENPLL_SW_NIC_CLK
+    chimp	genpll_sw	4	BCM_NS2_GENPLL_SW_CHIMP_CLK
+    port	genpll_sw	5	BCM_NS2_GENPLL_SW_PORT_CLK
+    sdio	genpll_sw	6	BCM_NS2_GENPLL_SW_SDIO_CLK
+
+    lcpll_ddr	crystal		0	BCM_NS2_LCPLL_DDR
+    pcie_sata_usb lcpll_ddr	1	BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
+    ddr		lcpll_ddr	2	BCM_NS2_LCPLL_DDR_DDR_CLK
+    ch2_unused	lcpll_ddr	3	BCM_NS2_LCPLL_DDR_CH2_UNUSED
+    ch3_unused	lcpll_ddr	4	BCM_NS2_LCPLL_DDR_CH3_UNUSED
+    ch4_unused	lcpll_ddr	5	BCM_NS2_LCPLL_DDR_CH4_UNUSED
+    ch5_unused	lcpll_ddr	6	BCM_NS2_LCPLL_DDR_CH5_UNUSED
+
+    lcpll_ports	crystal		0	BCM_NS2_LCPLL_PORTS
+    wan		lcpll_ports	1	BCM_NS2_LCPLL_PORTS_WAN_CLK
+    rgmii	lcpll_ports	2	BCM_NS2_LCPLL_PORTS_RGMII_CLK
+    ch2_unused	lcpll_ports	3	BCM_NS2_LCPLL_PORTS_CH2_UNUSED
+    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
+    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
+    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED
-- 
1.9.1

Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding

[Ray Jui]

Same as this patch. I thought device tree binding document should go
with the clock driver changes.

Strictly speaking, device tree binding document should always go before
the driver changes. In the binding document the DT interface is defined,
then changes are implemented in the driver.

Ray

On 10/13/2015 2:22 PM, Jon Mason wrote:
> Document the device tree bindings for Broadcom Northstar 2 architecture
> based clock controller
> 
> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> ---
>  .../bindings/clock/brcm,iproc-clocks.txt           | 48 ++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> index b3c3e9d..ede65a5 100644
> --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> @@ -160,3 +160,51 @@ Northstar Plus.  These clock IDs are defined in:
>      pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
>      sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
>      ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
> +
> +Northstar 2
> +-----------
> +PLL and leaf clock compatible strings for Northstar 2 are:
> +    "brcm,ns2-genpll-scr"
> +    "brcm,ns2-genpll-sw"
> +    "brcm,ns2-lcpll-ddr"
> +    "brcm,ns2-lcpll-ports"
> +
> +The following table defines the set of PLL/clock index and ID for Northstar 2.
> +These clock IDs are defined in:
> +    "include/dt-bindings/clock/bcm-ns2.h"
> +
> +    Clock	Source		Index	ID
> +    ---		-----		-----	---------
> +    crystal	N/A		N/A	N/A
> +
> +    genpll_scr	crystal		0	BCM_NS2_GENPLL_SCR
> +    scr		genpll_scr	1	BCM_NS2_GENPLL_SCR_SCR_CLK
> +    fs		genpll_scr	2	BCM_NS2_GENPLL_SCR_FS_CLK
> +    audio_ref	genpll_scr	3	BCM_NS2_GENPLL_SCR_AUDIO_CLK
> +    ch3_unused	genpll_scr	4	BCM_NS2_GENPLL_SCR_CH3_UNUSED
> +    ch4_unused	genpll_scr	5	BCM_NS2_GENPLL_SCR_CH4_UNUSED
> +    ch5_unused	genpll_scr	6	BCM_NS2_GENPLL_SCR_CH5_UNUSED
> +
> +    genpll_sw	crystal		0	BCM_NS2_GENPLL_SW
> +    rpe		genpll_sw	1	BCM_NS2_GENPLL_SW_RPE_CLK
> +    250		genpll_sw	2	BCM_NS2_GENPLL_SW_250_CLK
> +    nic		genpll_sw	3	BCM_NS2_GENPLL_SW_NIC_CLK
> +    chimp	genpll_sw	4	BCM_NS2_GENPLL_SW_CHIMP_CLK
> +    port	genpll_sw	5	BCM_NS2_GENPLL_SW_PORT_CLK
> +    sdio	genpll_sw	6	BCM_NS2_GENPLL_SW_SDIO_CLK
> +
> +    lcpll_ddr	crystal		0	BCM_NS2_LCPLL_DDR
> +    pcie_sata_usb lcpll_ddr	1	BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
> +    ddr		lcpll_ddr	2	BCM_NS2_LCPLL_DDR_DDR_CLK
> +    ch2_unused	lcpll_ddr	3	BCM_NS2_LCPLL_DDR_CH2_UNUSED
> +    ch3_unused	lcpll_ddr	4	BCM_NS2_LCPLL_DDR_CH3_UNUSED
> +    ch4_unused	lcpll_ddr	5	BCM_NS2_LCPLL_DDR_CH4_UNUSED
> +    ch5_unused	lcpll_ddr	6	BCM_NS2_LCPLL_DDR_CH5_UNUSED
> +
> +    lcpll_ports	crystal		0	BCM_NS2_LCPLL_PORTS
> +    wan		lcpll_ports	1	BCM_NS2_LCPLL_PORTS_WAN_CLK
> +    rgmii	lcpll_ports	2	BCM_NS2_LCPLL_PORTS_RGMII_CLK
> +    ch2_unused	lcpll_ports	3	BCM_NS2_LCPLL_PORTS_CH2_UNUSED
> +    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
> +    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
> +    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED
> 

Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding

[Jon Mason]

On Tue, Oct 13, 2015 at 03:24:52PM -0700, Ray Jui wrote:
> Same as this patch. I thought device tree binding document should go
> with the clock driver changes.
> 
> Strictly speaking, device tree binding document should always go before
> the driver changes. In the binding document the DT interface is defined,
> then changes are implemented in the driver.

I split them off this way due to the clk maintainer not wanting to
pull in any device tree changes.  Since the documentation is for the
device tree enties, it makes logical sense to me that they be in the
same device tree series.  If Stephen will pull these in with the clk
changes, I am more than happy to have it done by him :)

Thanks,
Jon

> 
> Ray
> 
> On 10/13/2015 2:22 PM, Jon Mason wrote:
> > Document the device tree bindings for Broadcom Northstar 2 architecture
> > based clock controller
> > 
> > Signed-off-by: Jon Mason <jonmason@broadcom.com>
> > ---
> >  .../bindings/clock/brcm,iproc-clocks.txt           | 48 ++++++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> > index b3c3e9d..ede65a5 100644
> > --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> > +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
> > @@ -160,3 +160,51 @@ Northstar Plus.  These clock IDs are defined in:
> >      pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
> >      sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
> >      ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
> > +
> > +Northstar 2
> > +-----------
> > +PLL and leaf clock compatible strings for Northstar 2 are:
> > +    "brcm,ns2-genpll-scr"
> > +    "brcm,ns2-genpll-sw"
> > +    "brcm,ns2-lcpll-ddr"
> > +    "brcm,ns2-lcpll-ports"
> > +
> > +The following table defines the set of PLL/clock index and ID for Northstar 2.
> > +These clock IDs are defined in:
> > +    "include/dt-bindings/clock/bcm-ns2.h"
> > +
> > +    Clock	Source		Index	ID
> > +    ---		-----		-----	---------
> > +    crystal	N/A		N/A	N/A
> > +
> > +    genpll_scr	crystal		0	BCM_NS2_GENPLL_SCR
> > +    scr		genpll_scr	1	BCM_NS2_GENPLL_SCR_SCR_CLK
> > +    fs		genpll_scr	2	BCM_NS2_GENPLL_SCR_FS_CLK
> > +    audio_ref	genpll_scr	3	BCM_NS2_GENPLL_SCR_AUDIO_CLK
> > +    ch3_unused	genpll_scr	4	BCM_NS2_GENPLL_SCR_CH3_UNUSED
> > +    ch4_unused	genpll_scr	5	BCM_NS2_GENPLL_SCR_CH4_UNUSED
> > +    ch5_unused	genpll_scr	6	BCM_NS2_GENPLL_SCR_CH5_UNUSED
> > +
> > +    genpll_sw	crystal		0	BCM_NS2_GENPLL_SW
> > +    rpe		genpll_sw	1	BCM_NS2_GENPLL_SW_RPE_CLK
> > +    250		genpll_sw	2	BCM_NS2_GENPLL_SW_250_CLK
> > +    nic		genpll_sw	3	BCM_NS2_GENPLL_SW_NIC_CLK
> > +    chimp	genpll_sw	4	BCM_NS2_GENPLL_SW_CHIMP_CLK
> > +    port	genpll_sw	5	BCM_NS2_GENPLL_SW_PORT_CLK
> > +    sdio	genpll_sw	6	BCM_NS2_GENPLL_SW_SDIO_CLK
> > +
> > +    lcpll_ddr	crystal		0	BCM_NS2_LCPLL_DDR
> > +    pcie_sata_usb lcpll_ddr	1	BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
> > +    ddr		lcpll_ddr	2	BCM_NS2_LCPLL_DDR_DDR_CLK
> > +    ch2_unused	lcpll_ddr	3	BCM_NS2_LCPLL_DDR_CH2_UNUSED
> > +    ch3_unused	lcpll_ddr	4	BCM_NS2_LCPLL_DDR_CH3_UNUSED
> > +    ch4_unused	lcpll_ddr	5	BCM_NS2_LCPLL_DDR_CH4_UNUSED
> > +    ch5_unused	lcpll_ddr	6	BCM_NS2_LCPLL_DDR_CH5_UNUSED
> > +
> > +    lcpll_ports	crystal		0	BCM_NS2_LCPLL_PORTS
> > +    wan		lcpll_ports	1	BCM_NS2_LCPLL_PORTS_WAN_CLK
> > +    rgmii	lcpll_ports	2	BCM_NS2_LCPLL_PORTS_RGMII_CLK
> > +    ch2_unused	lcpll_ports	3	BCM_NS2_LCPLL_PORTS_CH2_UNUSED
> > +    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
> > +    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
> > +    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED
> > 

Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding

[Ray Jui]

On 10/14/2015 8:44 AM, Jon Mason wrote:
> On Tue, Oct 13, 2015 at 03:24:52PM -0700, Ray Jui wrote:
>> Same as this patch. I thought device tree binding document should go
>> with the clock driver changes.
>>
>> Strictly speaking, device tree binding document should always go before
>> the driver changes. In the binding document the DT interface is defined,
>> then changes are implemented in the driver.
> 
> I split them off this way due to the clk maintainer not wanting to
> pull in any device tree changes.  Since the documentation is for the
> device tree enties, it makes logical sense to me that they be in the
> same device tree series.  If Stephen will pull these in with the clk
> changes, I am more than happy to have it done by him :)
> 
> Thanks,
> Jon

Yeah the clock maintainers do not pull in device tree changes like
*.dtsi and *.dts. But they do take changes including the binding
documents and clock driver changes. You can confirm with Stephen.

Thanks,

Ray

Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding

[Stephen Boyd]

On 10/14, Ray Jui wrote:
> 
> 
> On 10/14/2015 8:44 AM, Jon Mason wrote:
> > On Tue, Oct 13, 2015 at 03:24:52PM -0700, Ray Jui wrote:
> >> Same as this patch. I thought device tree binding document should go
> >> with the clock driver changes.
> >>
> >> Strictly speaking, device tree binding document should always go before
> >> the driver changes. In the binding document the DT interface is defined,
> >> then changes are implemented in the driver.
> > 
> > I split them off this way due to the clk maintainer not wanting to
> > pull in any device tree changes.  Since the documentation is for the
> > device tree enties, it makes logical sense to me that they be in the
> > same device tree series.  If Stephen will pull these in with the clk
> > changes, I am more than happy to have it done by him :)
> > 
> > Thanks,
> > Jon
> 
> Yeah the clock maintainers do not pull in device tree changes like
> *.dtsi and *.dts. But they do take changes including the binding
> documents and clock driver changes. You can confirm with Stephen.
> 

Yes we take bindings (I know I'm replying to an old patch).

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[RFC 5/5] ARM: dts: enable clock support for Broadcom NS2

[Jon Mason]

Add device tree entries for clock support for Broadcom Northstar 2 SoC

Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
 arch/arm64/boot/dts/broadcom/ns2.dtsi | 93 ++++++++++++++++++++++++++++++++---
 1 file changed, 86 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 3c92d92..c632f3b 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/bcm-ns2.h>
 
 /memreserve/ 0x84b00000 0x00000008;
 
@@ -89,25 +90,103 @@
 			      IRQ_TYPE_EDGE_RISING)>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		iprocmed: iprocmed {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+
+		iprocslow: iprocslow {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
+		ranges = <0 0 0x65000000 0x01130100>;
+
+		lcpll_ddr: lcpll_ddr@001d058 {
+			#clock-cells = <1>;
+			compatible = "brcm,ns2-lcpll-ddr";
+			reg = <0x001d058 0x20>,
+			      <0x001c020 0x4>,
+			      <0x001d04c 0x4>;
+			clocks = <&osc>;
+			clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+					     "ddr", "ddr_ch2_unused",
+					     "ddr_ch3_unused", "ddr_ch4_unused",
+					     "ddr_ch5_unused";
+		};
+
+		lcpll_ports: lcpll_ports@1d078 {
+			#clock-cells = <1>;
+			compatible = "brcm,ns2-lcpll-ports";
+			reg = <0x001d078 0x20>,
+			      <0x001c020 0x4>,
+			      <0x001d054 0x4>;
+			clocks = <&osc>;
+			clock-output-names = "lcpll_ports", "wan", "rgmii",
+					     "ports_ch2_unused",
+					     "ports_ch3_unused",
+					     "ports_ch4_unused",
+					     "ports_ch5_unused";
+		};
+
+		genpll_scr: genpll_scr@001d098 {
+			#clock-cells = <1>;
+			compatible = "brcm,ns2-genpll-scr";
+			reg = <0x001d098 0x32>,
+			      <0x001c020 0x4>,
+			      <0x001d044 0x4>;
+			clocks = <&osc>;
+			clock-output-names = "genpll_scr", "scr", "fs",
+					     "audio_ref", "scr_ch3_unused",
+					     "scr_ch4_unused", "scr_ch5_unused";
+		};
+
+		genpll_sw: genpll_sw@001d0c4 {
+			#clock-cells = <1>;
+			compatible = "brcm,ns2-genpll-sw";
+			reg = <0x001d0c4 0x32>,
+			      <0x001c020 0x4>,
+			      <0x001d044 0x4>;
+			clocks = <&osc>;
+			clock-output-names = "genpll_sw", "rpe", "250", "nic",
+					     "chimp", "port", "sdio";
+		};
 
-		gic: interrupt-controller@65210000 {
+		gic: interrupt-controller@0210000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
 			interrupt-controller;
-			reg = <0x65210000 0x1000>,
-			      <0x65220000 0x1000>,
-			      <0x65240000 0x2000>,
-			      <0x65260000 0x1000>;
+			reg = <0x0210000 0x1000>,
+			      <0x0220000 0x1000>,
+			      <0x0240000 0x2000>,
+			      <0x0260000 0x1000>;
 		};
 
-		uart3: serial@66130000 {
+		uart3: serial@1130000 {
 			compatible = "snps,dw-apb-uart";
-			reg = <0x66130000 0x100>;
+			reg = <0x1130000 0x100>;
 			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-- 
1.9.1