[PATCH v4 0/8] Add SPDIF support for rockchip

[PATCH v4 0/8] Add SPDIF support for rockchip

[Sjoerd Simons]

This patchset adds support for the Rockchip SPDIF transceiver as present
on RK3066, RK3188 and RK3288 boards and enables it on a Radxa rock pro.
Tested on a Radxa Rock Pro board and Radxa Rock 2 Square board.

Quite a few changes since v3 (mostly based on review comment). One
important addition is proper RK3288 SoC support; While according to the
documentation it has 2 SPDIF "solutions" with the default being the old
one, this variation doesn't actually work.. So support has been added
to switch to the new SPDIF solution on RK3288.

Changes in v4:
- Require rockchip,grf on RK3288 as the 8 channel solution has to be
  selected on that SoC
- Make the compatibility string one of a known list rather then
  requiring a precise list of options.
- Change the clock names to hclk and mclk instead of spdif_hclk and
  spdif_mclk to better match the implementation and data sheets.
- Use hclk and mclk as the clock names matching the update devicetree
  documentation
- Drop something useless to_info function
- Open-code tx control in rk_spdif_trigge
- Use devm_regmap_init_mmio_clk to allow the regmap subsystem to manage
  the hclk as needed
- Use a more conventionale pm setup (turn everything on,
  mark the device as active, enable pm and request the device to go
  idle)
- re-add the platfrorm:rockchip-spdif module alias
- Also manage the hclk in the PM callbacks
- Check the return code of clk_set_rate
- Switch to the 8 channel spdif solutions on RK3288
- Add support for 192khz audio rate
- Adjust clock names to match the new names (hclk/mclk)

Changes in v3:
- Fix typos in commit message
- Resent patches to a more complete list of maintainers.

Changes in v2:
- Remove platform: module alias as it was unused
- Call MODULE_DEVICE_TABLE(of, ) right after the of match table
- use rk_spdif as a prefix consistenly throughout the driver
- Check return code of regmap_update and bubble it up
- Sort the spdif node properties
- Drop the 0x prefix from the node name
- Rename the spdif@ node to sound@

Sjoerd Simons (8):
  ASoC: dt-bindings: add rockchip tranceiver bindings
  ASoC: rockchip: Add rockchip SPDIF transceiver driver
  ARM: dts: rockchip: Add SPDIF transceiver for RK3188
  ARM: dts: rockchip: Add SPDIF optical out on Radxa Rock
  clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
  ARM: dts: rockchip: Add SPDIF transceiver for RK3288
  ARM: dts: rockchip: Add SPDIF optical out on Radxa Rock2 Square
  ARM: multi_v7_defconfig: Add rockchip audio support

 .../devicetree/bindings/sound/rockchip-spdif.txt   |  44 +++
 arch/arm/boot/dts/rk3188-radxarock.dts             |  19 +
 arch/arm/boot/dts/rk3188.dtsi                      |  22 ++
 arch/arm/boot/dts/rk3288-rock2-square.dts          |  18 +
 arch/arm/boot/dts/rk3288.dtsi                      |  23 ++
 arch/arm/configs/multi_v7_defconfig                |   5 +
 drivers/clk/rockchip/clk-rk3288.c                  |  16 +-
 sound/soc/rockchip/Kconfig                         |   8 +
 sound/soc/rockchip/Makefile                        |   2 +
 sound/soc/rockchip/rockchip_spdif.c                | 409 +++++++++++++++++++++
 sound/soc/rockchip/rockchip_spdif.h                |  63 ++++
 11 files changed, 621 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/rockchip-spdif.txt
 create mode 100644 sound/soc/rockchip/rockchip_spdif.c
 create mode 100644 sound/soc/rockchip/rockchip_spdif.h

-- 
2.6.1

[PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

[Sjoerd Simons]

The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
SoCs only feed those clocks, allow those clocks to change their parents
all the way up the hierarchy.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 90c1c9b..4e90252 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -317,25 +317,25 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
 	MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
 			RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
-	COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
+	COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
 			RK3288_CLKGATE_CON(4), 4, GFLAGS),
-	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
+	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(9), 0,
 			RK3288_CLKGATE_CON(4), 5, GFLAGS,
-		MUX(0, "spdif_mux", mux_spdif_p, 0,
+		MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
 				RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)),
-	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 0,
+	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
 			RK3288_CLKGATE_CON(4), 6, GFLAGS),
-	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
+	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
 			RK3288_CLKGATE_CON(4), 7, GFLAGS),
-	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
+	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(41), 0,
 			RK3288_CLKGATE_CON(4), 8, GFLAGS,
-		MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, 0,
+		MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 				RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)),
-	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 0,
+	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
 			RK3288_CLKGATE_CON(4), 9, GFLAGS),
 
 	GATE(0, "sclk_acc_efuse", "xin24m", 0,
-- 
2.6.1

Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

[Heiko Stuebner]

Am Donnerstag, 8. Oktober 2015, 15:31:16 schrieb Sjoerd Simons:
> The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
> SoCs only feed those clocks, allow those clocks to change their parents
> all the way up the hierarchy.
> 
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>

Just as comment, if I'm seeing that right, this patch needs "clk: rockchip: 
handle mux dependency of fractional dividers" and friends [0] to apply and 
also actually handle the fractional dividers correctly.

For the clock change itself:
Reviewed-by: Heiko Stuebner <heiko@sntech.de>


Heiko

[0] http://lists.infradead.org/pipermail/linux-rockchip/2015-August/003930.html


> ---
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index 90c1c9b..4e90252 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -317,25 +317,25 @@ static struct rockchip_clk_branch
> rk3288_clk_branches[] __initdata = {
> 
>  	MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
>  			RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
> -	COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
> +	COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
>  			RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
>  			RK3288_CLKGATE_CON(4), 4, GFLAGS),
> -	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
> +	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
>  			RK3288_CLKSEL_CON(9), 0,
>  			RK3288_CLKGATE_CON(4), 5, GFLAGS,
> -		MUX(0, "spdif_mux", mux_spdif_p, 0,
> +		MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
>  				RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)),
> -	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 0,
> +	GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
>  			RK3288_CLKGATE_CON(4), 6, GFLAGS),
> -	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
> +	COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
>  			RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
>  			RK3288_CLKGATE_CON(4), 7, GFLAGS),
> -	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
> +	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre",
> CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(41), 0,
>  			RK3288_CLKGATE_CON(4), 8, GFLAGS,
> -		MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, 0,
> +		MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
>  				RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)),
> -	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 0,
> +	GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux",
> CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 9, GFLAGS),
> 
>  	GATE(0, "sclk_acc_efuse", "xin24m", 0,

Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

[Sjoerd Simons]

Hey Heiko,

On Thu, 2015-10-08 at 17:10 +0200, Heiko Stuebner wrote:
> Am Donnerstag, 8. Oktober 2015, 15:31:16 schrieb Sjoerd Simons:
> > The clock branches leading to sclk_spdif and sclk_spdif_8ch on
> > RK3288
> > SoCs only feed those clocks, allow those clocks to change their
> > parents
> > all the way up the hierarchy.
> >=20
> > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>=20
> Just as comment, if I'm seeing that right, this patch needs "clk:
> rockchip:=20
> handle mux dependency of fractional dividers" and friends [0] to
> apply and=20
> also actually handle the fractional dividers correctly.
>=20
> For the clock change itself:
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Oh sorry yes, i completely forgot to at that as note on this patch
(series). These are on top of your series as those are required to make
things actually work as expected.=20

Which reminds me, i was wondering how to best move that forward. Could
you pick this one up to include it in the next round of your series?
(Otherwise i'm happy to rebase it once you do a v2)

>=20
> Heiko
>=20
> [0] http://lists.infradead.org/pipermail/linux-rockchip/2015-August/0
> 03930.html


--=20
Sjoerd Simons
Collabora Ltd.

Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

[Heiko Stübner]

Hi Sjoerd,

Am Freitag, 9. Oktober 2015, 13:35:55 schrieb Sjoerd Simons:
> On Thu, 2015-10-08 at 17:10 +0200, Heiko Stuebner wrote:
> > Am Donnerstag, 8. Oktober 2015, 15:31:16 schrieb Sjoerd Simons:
> > > The clock branches leading to sclk_spdif and sclk_spdif_8ch on
> > > RK3288
> > > SoCs only feed those clocks, allow those clocks to change their
> > > parents
> > > all the way up the hierarchy.
> > > 
> > > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> > 
> > Just as comment, if I'm seeing that right, this patch needs "clk:
> > rockchip:
> > handle mux dependency of fractional dividers" and friends [0] to
> > apply and
> > also actually handle the fractional dividers correctly.
> > 
> > For the clock change itself:
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> 
> Oh sorry yes, i completely forgot to at that as note on this patch
> (series). These are on top of your series as those are required to make
> things actually work as expected.
> 
> Which reminds me, i was wondering how to best move that forward. Could
> you pick this one up to include it in the next round of your series?
> (Otherwise i'm happy to rebase it once you do a v2)

I guess that will depend on how the core series gets handled. Aka if there 
needs to be a v2 (depending on the clock maintainers) I can pick that up as 
part of it. Otherwise we'll just need to ping the clock-maintainers separately 
on this patch if necessary.


Heiko

Re: [PATCH v4 0/8] Add SPDIF support for rockchip

[Heiko Stübner]

Am Donnerstag, 8. Oktober 2015, 15:31:11 schrieb Sjoerd Simons:
> This patchset adds support for the Rockchip SPDIF transceiver as present
> on RK3066, RK3188 and RK3288 boards and enables it on a Radxa rock pro.
> Tested on a Radxa Rock Pro board and Radxa Rock 2 Square board.
> 
> Quite a few changes since v3 (mostly based on review comment). One
> important addition is proper RK3288 SoC support; While according to the
> documentation it has 2 SPDIF "solutions" with the default being the old
> one, this variation doesn't actually work.. So support has been added
> to switch to the new SPDIF solution on RK3288.

[...]

> Sjoerd Simons (8):
>   ASoC: dt-bindings: add rockchip tranceiver bindings
>   ASoC: rockchip: Add rockchip SPDIF transceiver driver
>   ARM: dts: rockchip: Add SPDIF transceiver for RK3188
>   ARM: dts: rockchip: Add SPDIF optical out on Radxa Rock
>   clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
>   ARM: dts: rockchip: Add SPDIF transceiver for RK3288
>   ARM: dts: rockchip: Add SPDIF optical out on Radxa Rock2 Square
>   ARM: multi_v7_defconfig: Add rockchip audio support

After Mark took the two ASoC-specific patches, I've now picked up the 4 dts 
patches, after removing the #address- and #size-cells lines from them.

Sjoerd, are you sending a followup patch to Mark to also drop them from the 
binding doc?

Hopefully the clock patch will also find its way into the clock tree, together 
with the base series for the frac dividers.

And I guess we'll need to prod the armsoc-guys to take the defconfig change 
too :-)


Heiko

Re: [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent

[Michael Turquette]

Quoting Heiko St=C3=BCbner (2015-10-11 03:43:27)
> Hi Sjoerd,
> =

> Am Freitag, 9. Oktober 2015, 13:35:55 schrieb Sjoerd Simons:
> > On Thu, 2015-10-08 at 17:10 +0200, Heiko Stuebner wrote:
> > > Am Donnerstag, 8. Oktober 2015, 15:31:16 schrieb Sjoerd Simons:
> > > > The clock branches leading to sclk_spdif and sclk_spdif_8ch on
> > > > RK3288
> > > > SoCs only feed those clocks, allow those clocks to change their
> > > > parents
> > > > all the way up the hierarchy.
> > > > =

> > > > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> > > =

> > > Just as comment, if I'm seeing that right, this patch needs "clk:
> > > rockchip:
> > > handle mux dependency of fractional dividers" and friends [0] to
> > > apply and
> > > also actually handle the fractional dividers correctly.
> > > =

> > > For the clock change itself:
> > > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> > =

> > Oh sorry yes, i completely forgot to at that as note on this patch
> > (series). These are on top of your series as those are required to make
> > things actually work as expected.
> > =

> > Which reminds me, i was wondering how to best move that forward. Could
> > you pick this one up to include it in the next round of your series?
> > (Otherwise i'm happy to rebase it once you do a v2)
> =

> I guess that will depend on how the core series gets handled. Aka if ther=
e =

> needs to be a v2 (depending on the clock maintainers) I can pick that up =
as =

> part of it. Otherwise we'll just need to ping the clock-maintainers separ=
ately =

> on this patch if necessary.

I've spoken with Heiko on irc about v2 about using the coordinated clock
rates patches for handling the mux/fractional dividers thing. I'd prefer
to use the ccr approach, which puts a delay on that series.

Is there anything wrong with merging this patch #5/8 as-is? Will the
struct clk_core.rate accounting not match the hardware if we set
CLK_SET_PARENT_RATE on these clocks?

Regards,
Mike

> =

> =

> Heiko
>=20