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Date: Mon, 25 Jan 2016 13:47:23 +0100
From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Mike Turquette <mturquette@baylibre.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Alexandre Courbot <gnurou@gmail.com>, linux-clk@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [Patch V2 8/9] clk: tegra: pll: Fix typos around clearing plle
 bits during enable
Message-ID: <20160125124723.GM20452@ulmo.nvidia.com>
References: <1452799478-14791-1-git-send-email-rklein@nvidia.com>
 <1452799478-14791-9-git-send-email-rklein@nvidia.com>
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On Thu, Jan 14, 2016 at 02:24:37PM -0500, Rhyland Klein wrote:
> While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
> PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
> them. This patch fixes both places where we incorrectly set instead
> of cleared those bits.
>=20
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
>  drivers/clk/tegra/clk-pll.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied, thanks.

Thierry

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