From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Alexandre Courbot <gnurou@gmail.com>,
Jon Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
Bill Huang <bilhuang@nvidia.com>
Subject: Re: [PATCH] clk: tegra210: Add SLCG override gate clocks
Date: Mon, 14 Mar 2016 17:05:51 +0100 [thread overview]
Message-ID: <20160314160551.GA21898@ulmo.nvidia.com> (raw)
In-Reply-To: <1457638685-31007-1-git-send-email-rklein@nvidia.com>
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On Thu, Mar 10, 2016 at 02:38:05PM -0500, Rhyland Klein wrote:
> From: Bill Huang <bilhuang@nvidia.com>
>
> Add some SLCG (Second Level Clock Gating) override clocks to control
> gating and un-gating their logics.
>
> Signed-off-by: Bill Huang <bilhuang@nvidia.com>
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
> drivers/clk/tegra/clk-id.h | 16 ++++++
> drivers/clk/tegra/clk-tegra210.c | 91 ++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/tegra210-car.h | 32 +++++------
> 3 files changed, 123 insertions(+), 16 deletions(-)
There's no rationale given here about why we need this. What will these
second level clock gates be used for? Why do we need these (seemingly)
duplicate clock entries.
Thierry
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next prev parent reply other threads:[~2016-03-14 16:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-10 19:38 [PATCH] clk: tegra210: Add SLCG override gate clocks Rhyland Klein
2016-03-14 16:05 ` Thierry Reding [this message]
2016-03-14 16:08 ` Rhyland Klein
2016-03-15 8:40 ` Jon Hunter
2016-03-25 18:21 ` Rhyland Klein
2016-04-12 15:20 ` Thierry Reding
2016-04-12 17:41 ` Jon Hunter
2016-04-22 11:12 ` Thierry Reding
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