[PATCH 0/2] Rework clk/vt8500 wm8650_find_pll_bits()

[PATCH 0/2] Rework clk/vt8500 wm8650_find_pll_bits()

[Roman Volkov]

From: Roman Volkov <rvolkov@v1ros.org>

Hi Arnd and others,

This patch finally removes the warnings from GCC about possibly uninitialized
variables 'best_div2', 'best_div1', and 'best_mul'. Also one of the functions
is reworked, so that the algorithm is much easier. This is to continue the
work started in [1].

This code is tested on WM8650. Also the testing app was used in user-mode to
check possible values and performance [2].

[1] https://lkml.org/lkml/2016/2/1/149
[2] https://github.com/v1ron/vt8500-clkrange

Thanks,
Roman Volkov (2):
  clk/vt8500: Rework wm8650_find_pll_bits()
  clk/vt8500: Fix compilation warnings

 drivers/clk/clk-vt8500.c | 81 +++++++++++++++++++++++-------------------------
 1 file changed, 39 insertions(+), 42 deletions(-)

-- 
2.8.0

[PATCH 1/2] clk/vt8500: Rework wm8650_find_pll_bits()

[Roman Volkov]

From: Roman Volkov <rvolkov@v1ros.org>

WM8650 has the following limitation in the clock architecture:

600MHz >= (M * parent) / P >= 300MHz

Where M is multiplier and P is divisor 1 (refer to the source code
comment). This information can be found in the WMT's GPL source. The
algorithm from this change is optimized, performance increase is about
10000 times per the user-mode testing application.

The following GCC warnings are fixed inside the function:

'best_div2', 'best_div1', 'best_mul' may be used uninitialized in
this function [-Wmaybe-uninitialized]

Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values")
Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
---
 drivers/clk/clk-vt8500.c | 77 +++++++++++++++++++++++-------------------------
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index b0f76a84f1e9..77650f19a9b6 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -383,52 +383,49 @@ static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	return 0;
 }
 
-static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
-				u32 *multiplier, u32 *divisor1, u32 *divisor2)
+/*
+ * M * parent [O1] => / P [O2] => / D [O3]
+ * Where O1 is 900MHz...3GHz;
+ * O2 is 600MHz >= (M * parent) / P >= 300MHz;
+ * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
+ * Possible ranges (O3):
+ * D = 8: 37,5MHz...75MHz
+ * D = 4: 75MHz...150MHz
+ * D = 2: 150MHz...300MHz
+ * D = 1: 300MHz...600MHz
+ */
+static int wm8650_find_pll_bits(unsigned long rate,
+	unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
+	u32 *divisor2)
 {
-	u32 mul, div1;
-	int div2;
-	u32 best_mul, best_div1, best_div2;
-	unsigned long tclk, rate_err, best_err;
+	unsigned long O1, min_err, rate_err;
 
-	best_err = (unsigned long)-1;
-
-	/* Find the closest match (lower or equal to requested) */
-	for (div1 = 5; div1 >= 3; div1--)
-		for (div2 = 3; div2 >= 0; div2--)
-			for (mul = 3; mul <= 1023; mul++) {
-				tclk = parent_rate * mul / (div1 * (1 << div2));
-				if (tclk > rate)
-					continue;
-				/* error will always be +ve */
-				rate_err = rate - tclk;
-				if (rate_err == 0) {
-					*multiplier = mul;
-					*divisor1 = div1;
-					*divisor2 = div2;
-					return 0;
-				}
-
-				if (rate_err < best_err) {
-					best_err = rate_err;
-					best_mul = mul;
-					best_div1 = div1;
-					best_div2 = div2;
-				}
-			}
-
-	if (best_err == (unsigned long)-1) {
-		pr_warn("%s: impossible rate %lu\n", __func__, rate);
+	if (!parent_rate || (rate < 37500000) || (rate > 600000000))
 		return -EINVAL;
+
+	*divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
+					   rate <= 300000000 ? 1 : 0;
+	/*
+	 * Divisor P cannot be calculated. Test all divisors and find where M
+	 * will be as close as possible to the requested rate.
+	 */
+	min_err = ULONG_MAX;
+	for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
+		O1 = rate * *divisor1 * (1 << (*divisor2));
+		rate_err = O1 % parent_rate;
+		if (rate_err < min_err) {
+			*multiplier = O1 / parent_rate;
+			if (rate_err == 0)
+				return 0;
+
+			min_err = rate_err;
+		}
 	}
 
-	/* if we got here, it wasn't an exact match */
-	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
-							rate - best_err);
-	*multiplier = best_mul;
-	*divisor1 = best_div1;
-	*divisor2 = best_div2;
+	if ((*multiplier < 3) || (*multiplier > 1023))
+		return -EINVAL;
 
+	pr_warn("%s: rate error is %lu\n", __func__, min_err);
 	return 0;
 }
 
-- 
2.8.0

[PATCH 2/2] clk/vt8500: Fix compilation warnings

[Roman Volkov]

From: Roman Volkov <rvolkov@v1ros.org>

GCC 5.3.0 still throws the following warnings for functions
wm8750_find_pll_bits() and wm8850_find_pll_bits():

warning: 'best_div2' may be used uninitialized in this function
warning: 'best_div1' may be used uninitialized in this function
warning: 'best_mul' may be used uninitialized in this function

These warnings are false positives, the variables are controlled
by checking the value of the variable 'best_err' which is -1 by
default. It is safe to initialize all these variables to zero.

Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values")
Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
---
 drivers/clk/clk-vt8500.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 77650f19a9b6..7c970d7c0a6a 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -461,7 +461,7 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 {
 	u32 mul;
 	int div1, div2;
-	u32 best_mul, best_div1, best_div2;
+	u32 best_mul = 0, best_div1 = 0, best_div2 = 0;
 	unsigned long tclk, rate_err, best_err;
 
 	best_err = (unsigned long)-1;
@@ -513,7 +513,7 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 {
 	u32 mul;
 	int div1, div2;
-	u32 best_mul, best_div1, best_div2;
+	u32 best_mul = 0, best_div1 = 0, best_div2 = 0;
 	unsigned long tclk, rate_err, best_err;
 
 	best_err = (unsigned long)-1;
-- 
2.8.0

Re: [PATCH 2/2] clk/vt8500: Fix compilation warnings

[Arnd Bergmann]

On Tuesday, May 24, 2016 11:07:53 PM CEST Roman Volkov wrote:
> From: Roman Volkov <rvolkov@v1ros.org>
>=20
> GCC 5.3.0 still throws the following warnings for functions
> wm8750_find_pll_bits() and wm8850_find_pll_bits():
>=20
> warning: 'best_div2' may be used uninitialized in this function
> warning: 'best_div1' may be used uninitialized in this function
> warning: 'best_mul' may be used uninitialized in this function
>=20
> These warnings are false positives, the variables are controlled
> by checking the value of the variable 'best_err' which is -1 by
> default. It is safe to initialize all these variables to zero.
>=20
> Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values")
> Signed-off-by: Roman Volkov <rvolkov@v1ros.org>

With gcc-5.3 and linux-4.7-rc1, they should be gone now (no longer
warning about this with gcov enabled), but I still get them with
gcc-4.9.

> diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
> index 77650f19a9b6..7c970d7c0a6a 100644
> --- a/drivers/clk/clk-vt8500.c
> +++ b/drivers/clk/clk-vt8500.c
> @@ -461,7 +461,7 @@ static int wm8750_find_pll_bits(unsigned long rate, u=
nsigned long parent_rate,
>  {
>  	u32 mul;
>  	int div1, div2;
> -	u32 best_mul, best_div1, best_div2;
> +	u32 best_mul =3D 0, best_div1 =3D 0, best_div2 =3D 0;
>  	unsigned long tclk, rate_err, best_err;
> =20
>  	best_err =3D (unsigned long)-1;
> @@ -513,7 +513,7 @@ static int wm8850_find_pll_bits(unsigned long rate, u=
nsigned long parent_rate,
>  {
>  	u32 mul;
>  	int div1, div2;
> -	u32 best_mul, best_div1, best_div2;
> +	u32 best_mul =3D 0, best_div1 =3D 0, best_div2 =3D 0;
>  	unsigned long tclk, rate_err, best_err;
> =20
>  	best_err =3D (unsigned long)-1;
>=20

I see you only patch two instances but not the third one. I think
we should do it consistently at least.

Coincidentally, I've just done another patch for this myself, since
it's the last gcc-4.9 warning we get in linux-4.7.

My version below

commit a38daeb34a2dc9d39ee1f153244cfcd83e865e0d
Author: Arnd Bergmann <arnd@arndb.de>
Date:   Tue May 31 10:41:26 2016 +0200

clk: vt8500: fix gcc-4.9 warnings

This fixes some false positive warnings we get with older compiler
versions:

clk-vt8500.c: In function =E2=80=98wm8650_find_pll_bits=E2=80=99:
clk-vt8500.c:430:12: =E2=80=98best_div2=E2=80=99 may be used uninitialized =
in this function
clk-vt8500.c:429:12: =E2=80=98best_div1=E2=80=99 may be used uninitialized =
in this function
clk-vt8500.c:428:14: =E2=80=98best_mul=E2=80=99 may be used uninitialized i=
n this function
clk-vt8500.c: In function =E2=80=98wm8750_find_pll_bits=E2=80=99:
clk-vt8500.c:509:12: =E2=80=98best_div2=E2=80=99 may be used uninitialized =
in this function
clk-vt8500.c:508:12: =E2=80=98best_div1=E2=80=99 may be used uninitialized =
in this function
clk-vt8500.c:507:14: =E2=80=98best_mul=E2=80=99 may be used uninitialized i=
n this function
clk-vt8500.c: In function =E2=80=98wm8850_find_pll_bits=E2=80=99:
clk-vt8500.c:560:12: =E2=80=98best_div2=E2=80=99 may be used uninitialized =
in this function
clk-vt8500.c:559:12: =E2=80=98best_div1=E2=80=99 may be used uninitialized =
in this function
clk-vt8500.c:558:14: =E2=80=98best_mul=E2=80=99 may be used uninitialized i=
n this function

As the local variables are only use for temporaries, we can just
as well assign the final values directly, which also makes the
code slightly shorter.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index b0f76a84f1e9..d5a3453970d0 100644
=2D-- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -388,7 +388,6 @@ static int wm8650_find_pll_bits(unsigned long rate, uns=
igned long parent_rate,
 {
 	u32 mul, div1;
 	int div2;
=2D	u32 best_mul, best_div1, best_div2;
 	unsigned long tclk, rate_err, best_err;
=20
 	best_err =3D (unsigned long)-1;
@@ -411,9 +410,9 @@ static int wm8650_find_pll_bits(unsigned long rate, uns=
igned long parent_rate,
=20
 				if (rate_err < best_err) {
 					best_err =3D rate_err;
=2D					best_mul =3D mul;
=2D					best_div1 =3D div1;
=2D					best_div2 =3D div2;
+					*multiplier =3D mul;
+					*divisor1 =3D div1;
+					*divisor2 =3D div2;
 				}
 			}
=20
@@ -425,10 +424,6 @@ static int wm8650_find_pll_bits(unsigned long rate, un=
signed long parent_rate,
 	/* if we got here, it wasn't an exact match */
 	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 							rate - best_err);
=2D	*multiplier =3D best_mul;
=2D	*divisor1 =3D best_div1;
=2D	*divisor2 =3D best_div2;
=2D
 	return 0;
 }
=20
@@ -464,7 +459,6 @@ static int wm8750_find_pll_bits(unsigned long rate, uns=
igned long parent_rate,
 {
 	u32 mul;
 	int div1, div2;
=2D	u32 best_mul, best_div1, best_div2;
 	unsigned long tclk, rate_err, best_err;
=20
 	best_err =3D (unsigned long)-1;
@@ -488,9 +482,9 @@ static int wm8750_find_pll_bits(unsigned long rate, uns=
igned long parent_rate,
=20
 				if (rate_err < best_err) {
 					best_err =3D rate_err;
=2D					best_mul =3D mul;
=2D					best_div1 =3D div1;
=2D					best_div2 =3D div2;
+					*multiplier =3D mul;
+					*divisor1 =3D div1;
+					*divisor2 =3D div2;
 				}
 			}
=20
@@ -503,10 +497,7 @@ static int wm8750_find_pll_bits(unsigned long rate, un=
signed long parent_rate,
 	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 							rate - best_err);
=20
=2D	*filter =3D wm8750_get_filter(parent_rate, best_div1);
=2D	*multiplier =3D best_mul;
=2D	*divisor1 =3D best_div1;
=2D	*divisor2 =3D best_div2;
+	*filter =3D wm8750_get_filter(parent_rate, *divisor1);
=20
 	return 0;
 }
@@ -516,7 +507,6 @@ static int wm8850_find_pll_bits(unsigned long rate, uns=
igned long parent_rate,
 {
 	u32 mul;
 	int div1, div2;
=2D	u32 best_mul, best_div1, best_div2;
 	unsigned long tclk, rate_err, best_err;
=20
 	best_err =3D (unsigned long)-1;
@@ -540,9 +530,9 @@ static int wm8850_find_pll_bits(unsigned long rate, uns=
igned long parent_rate,
=20
 				if (rate_err < best_err) {
 					best_err =3D rate_err;
=2D					best_mul =3D mul;
=2D					best_div1 =3D div1;
=2D					best_div2 =3D div2;
+					*multiplier =3D mul;
+					*divisor1 =3D div1;
+					*divisor2 =3D div2;
 				}
 			}
=20
@@ -555,10 +545,6 @@ static int wm8850_find_pll_bits(unsigned long rate, un=
signed long parent_rate,
 	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 							rate - best_err);
=20
=2D	*multiplier =3D best_mul;
=2D	*divisor1 =3D best_div1;
=2D	*divisor2 =3D best_div2;
=2D
 	return 0;
 }
=20

Re: [PATCH 2/2] clk/vt8500: Fix compilation warnings

[Roman Volkov]

=D0=92 Tue, 31 May 2016 12:51:55 +0200
Arnd Bergmann <arnd@arndb.de> =D0=BF=D0=B8=D1=88=D0=B5=D1=82:

> On Tuesday, May 24, 2016 11:07:53 PM CEST Roman Volkov wrote:
> > From: Roman Volkov <rvolkov@v1ros.org>
> >=20
> > GCC 5.3.0 still throws the following warnings for functions
> > wm8750_find_pll_bits() and wm8850_find_pll_bits():
> >=20
> > warning: 'best_div2' may be used uninitialized in this function
> > warning: 'best_div1' may be used uninitialized in this function
> > warning: 'best_mul' may be used uninitialized in this function
> >=20
> > These warnings are false positives, the variables are controlled
> > by checking the value of the variable 'best_err' which is -1 by
> > default. It is safe to initialize all these variables to zero.
> >=20
> > Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values")
> > Signed-off-by: Roman Volkov <rvolkov@v1ros.org> =20
>=20
> With gcc-5.3 and linux-4.7-rc1, they should be gone now (no longer
> warning about this with gcov enabled), but I still get them with
> gcc-4.9.
>=20
> > diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
> > index 77650f19a9b6..7c970d7c0a6a 100644
> > --- a/drivers/clk/clk-vt8500.c
> > +++ b/drivers/clk/clk-vt8500.c
> > @@ -461,7 +461,7 @@ static int wm8750_find_pll_bits(unsigned long
> > rate, unsigned long parent_rate, {
> >  	u32 mul;
> >  	int div1, div2;
> > -	u32 best_mul, best_div1, best_div2;
> > +	u32 best_mul =3D 0, best_div1 =3D 0, best_div2 =3D 0;
> >  	unsigned long tclk, rate_err, best_err;
> > =20
> >  	best_err =3D (unsigned long)-1;
> > @@ -513,7 +513,7 @@ static int wm8850_find_pll_bits(unsigned long
> > rate, unsigned long parent_rate, {
> >  	u32 mul;
> >  	int div1, div2;
> > -	u32 best_mul, best_div1, best_div2;
> > +	u32 best_mul =3D 0, best_div1 =3D 0, best_div2 =3D 0;
> >  	unsigned long tclk, rate_err, best_err;
> > =20
> >  	best_err =3D (unsigned long)-1;
> >  =20
>=20
> I see you only patch two instances but not the third one. I think
> we should do it consistently at least.
>=20
> Coincidentally, I've just done another patch for this myself, since
> it's the last gcc-4.9 warning we get in linux-4.7.
>=20
> My version below
>=20
> commit a38daeb34a2dc9d39ee1f153244cfcd83e865e0d
> Author: Arnd Bergmann <arnd@arndb.de>
> Date:   Tue May 31 10:41:26 2016 +0200
>=20
> clk: vt8500: fix gcc-4.9 warnings
>=20
> This fixes some false positive warnings we get with older compiler
> versions:
>=20
> clk-vt8500.c: In function =E2=80=98wm8650_find_pll_bits=E2=80=99:
> clk-vt8500.c:430:12: =E2=80=98best_div2=E2=80=99 may be used uninitialize=
d in this
> function clk-vt8500.c:429:12: =E2=80=98best_div1=E2=80=99 may be used uni=
nitialized
> in this function clk-vt8500.c:428:14: =E2=80=98best_mul=E2=80=99 may be u=
sed
> uninitialized in this function clk-vt8500.c: In function
> =E2=80=98wm8750_find_pll_bits=E2=80=99: clk-vt8500.c:509:12: =E2=80=98bes=
t_div2=E2=80=99 may be used
> uninitialized in this function clk-vt8500.c:508:12: =E2=80=98best_div1=E2=
=80=99 may
> be used uninitialized in this function clk-vt8500.c:507:14:
> =E2=80=98best_mul=E2=80=99 may be used uninitialized in this function clk=
-vt8500.c:
> In function =E2=80=98wm8850_find_pll_bits=E2=80=99: clk-vt8500.c:560:12: =
=E2=80=98best_div2=E2=80=99
> may be used uninitialized in this function clk-vt8500.c:559:12:
> =E2=80=98best_div1=E2=80=99 may be used uninitialized in this function
> clk-vt8500.c:558:14: =E2=80=98best_mul=E2=80=99 may be used uninitialized=
 in this
> function
>=20
> As the local variables are only use for temporaries, we can just
> as well assign the final values directly, which also makes the
> code slightly shorter.
>=20
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>=20
> diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
> index b0f76a84f1e9..d5a3453970d0 100644
> --- a/drivers/clk/clk-vt8500.c
> +++ b/drivers/clk/clk-vt8500.c
> @@ -388,7 +388,6 @@ static int wm8650_find_pll_bits(unsigned long
> rate, unsigned long parent_rate, {
>  	u32 mul, div1;
>  	int div2;
> -	u32 best_mul, best_div1, best_div2;
>  	unsigned long tclk, rate_err, best_err;
> =20
>  	best_err =3D (unsigned long)-1;
> @@ -411,9 +410,9 @@ static int wm8650_find_pll_bits(unsigned long
> rate, unsigned long parent_rate,=20
>  				if (rate_err < best_err) {
>  					best_err =3D rate_err;
> -					best_mul =3D mul;
> -					best_div1 =3D div1;
> -					best_div2 =3D div2;
> +					*multiplier =3D mul;
> +					*divisor1 =3D div1;
> +					*divisor2 =3D div2;
>  				}
>  			}
> =20
> @@ -425,10 +424,6 @@ static int wm8650_find_pll_bits(unsigned long
> rate, unsigned long parent_rate, /* if we got here, it wasn't an
> exact match */ pr_warn("%s: requested rate %lu, found rate %lu\n",
> __func__, rate, rate - best_err);
> -	*multiplier =3D best_mul;
> -	*divisor1 =3D best_div1;
> -	*divisor2 =3D best_div2;
> -
>  	return 0;
>  }
> =20
> @@ -464,7 +459,6 @@ static int wm8750_find_pll_bits(unsigned long
> rate, unsigned long parent_rate, {
>  	u32 mul;
>  	int div1, div2;
> -	u32 best_mul, best_div1, best_div2;
>  	unsigned long tclk, rate_err, best_err;
> =20
>  	best_err =3D (unsigned long)-1;
> @@ -488,9 +482,9 @@ static int wm8750_find_pll_bits(unsigned long
> rate, unsigned long parent_rate,=20
>  				if (rate_err < best_err) {
>  					best_err =3D rate_err;
> -					best_mul =3D mul;
> -					best_div1 =3D div1;
> -					best_div2 =3D div2;
> +					*multiplier =3D mul;
> +					*divisor1 =3D div1;
> +					*divisor2 =3D div2;
>  				}
>  			}
> =20
> @@ -503,10 +497,7 @@ static int wm8750_find_pll_bits(unsigned long
> rate, unsigned long parent_rate, pr_warn("%s: requested rate %lu,
> found rate %lu\n", __func__, rate, rate - best_err);
> =20
> -	*filter =3D wm8750_get_filter(parent_rate, best_div1);
> -	*multiplier =3D best_mul;
> -	*divisor1 =3D best_div1;
> -	*divisor2 =3D best_div2;
> +	*filter =3D wm8750_get_filter(parent_rate, *divisor1);
> =20
>  	return 0;
>  }
> @@ -516,7 +507,6 @@ static int wm8850_find_pll_bits(unsigned long
> rate, unsigned long parent_rate, {
>  	u32 mul;
>  	int div1, div2;
> -	u32 best_mul, best_div1, best_div2;
>  	unsigned long tclk, rate_err, best_err;
> =20
>  	best_err =3D (unsigned long)-1;
> @@ -540,9 +530,9 @@ static int wm8850_find_pll_bits(unsigned long
> rate, unsigned long parent_rate,=20
>  				if (rate_err < best_err) {
>  					best_err =3D rate_err;
> -					best_mul =3D mul;
> -					best_div1 =3D div1;
> -					best_div2 =3D div2;
> +					*multiplier =3D mul;
> +					*divisor1 =3D div1;
> +					*divisor2 =3D div2;
>  				}
>  			}
> =20
> @@ -555,10 +545,6 @@ static int wm8850_find_pll_bits(unsigned long
> rate, unsigned long parent_rate, pr_warn("%s: requested rate %lu,
> found rate %lu\n", __func__, rate, rate - best_err);
> =20
> -	*multiplier =3D best_mul;
> -	*divisor1 =3D best_div1;
> -	*divisor2 =3D best_div2;
> -
>  	return 0;
>  }
> =20
>=20
>=20

Arnd, your version is fine for me. We may apply it instead.

As you can see, I attached another patch where the logic for WM8650 is
completely reworked. This patch also removes the warning, that is why
fixing the wm8650 function is not necessary.

What about the WM8650 enhancement? Can I apply it on top of your
changes?

Regards,
Roman

Re: [PATCH 2/2] clk/vt8500: Fix compilation warnings

[Arnd Bergmann]

On Tuesday, May 31, 2016 9:38:54 PM CEST Roman Volkov wrote:
> 
> Arnd, your version is fine for me. We may apply it instead.
> 
> As you can see, I attached another patch where the logic for WM8650 is
> completely reworked. This patch also removes the warning, that is why
> fixing the wm8650 function is not necessary.
> 
> What about the WM8650 enhancement? Can I apply it on top of your
> changes?

I think the easiest way is if you pick up my patch and submit it together
with your other patch as a series (keeping my From: line and adding your
Signed-off-by: below mine).

My patch should probably go first so we can get it into linux-4.7, while
I assume your other one is for 4.8? If we want both in 4.7, either order
is fine.

	Arnd

Re: [PATCH 2/2] clk/vt8500: Fix compilation warnings

[Stephen Boyd]

On 05/31, Arnd Bergmann wrote:
> On Tuesday, May 31, 2016 9:38:54 PM CEST Roman Volkov wrote:
> > 
> > Arnd, your version is fine for me. We may apply it instead.
> > 
> > As you can see, I attached another patch where the logic for WM8650 is
> > completely reworked. This patch also removes the warning, that is why
> > fixing the wm8650 function is not necessary.
> > 
> > What about the WM8650 enhancement? Can I apply it on top of your
> > changes?
> 
> I think the easiest way is if you pick up my patch and submit it together
> with your other patch as a series (keeping my From: line and adding your
> Signed-off-by: below mine).
> 
> My patch should probably go first so we can get it into linux-4.7, while
> I assume your other one is for 4.8? If we want both in 4.7, either order
> is fine.
> 

Yes please do this, but we'll just merge both for v4.8.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/2] Rework clk/vt8500 wm8650_find_pll_bits()

[Roman Volkov]

=D0=92 Tue, 24 May 2016 23:07:51 +0300
Roman Volkov <v1ron@mail.ru> =D0=BF=D0=B8=D1=88=D0=B5=D1=82:

> From: Roman Volkov <rvolkov@v1ros.org>
>=20
> Hi Arnd and others,
>=20
> This patch finally removes the warnings from GCC about possibly
> uninitialized variables 'best_div2', 'best_div1', and 'best_mul'.
> Also one of the functions is reworked, so that the algorithm is much
> easier. This is to continue the work started in [1].
>=20
> This code is tested on WM8650. Also the testing app was used in
> user-mode to check possible values and performance [2].
>=20
> [1] https://lkml.org/lkml/2016/2/1/149
> [2] https://github.com/v1ron/vt8500-clkrange
>=20
> Thanks,
> Roman Volkov (2):
>   clk/vt8500: Rework wm8650_find_pll_bits()
>   clk/vt8500: Fix compilation warnings
>=20
>  drivers/clk/clk-vt8500.c | 81
> +++++++++++++++++++++++------------------------- 1 file changed, 39
> insertions(+), 42 deletions(-)
>=20

Hi Stephen,

Do we need this change during this merge window?

Thanks,
Roman

Re: [PATCH 0/2] Rework clk/vt8500 wm8650_find_pll_bits()

[Stephen Boyd]

On 05/31, Roman Volkov wrote:
> В Tue, 24 May 2016 23:07:51 +0300
> Roman Volkov <v1ron@mail.ru> пишет:
> 
> > From: Roman Volkov <rvolkov@v1ros.org>
> > 
> > Hi Arnd and others,
> > 
> > This patch finally removes the warnings from GCC about possibly
> > uninitialized variables 'best_div2', 'best_div1', and 'best_mul'.
> > Also one of the functions is reworked, so that the algorithm is much
> > easier. This is to continue the work started in [1].
> > 
> > This code is tested on WM8650. Also the testing app was used in
> > user-mode to check possible values and performance [2].
> > 
> > [1] https://lkml.org/lkml/2016/2/1/149
> > [2] https://github.com/v1ron/vt8500-clkrange
> > 
> > Thanks,
> > Roman Volkov (2):
> >   clk/vt8500: Rework wm8650_find_pll_bits()
> >   clk/vt8500: Fix compilation warnings
> > 
> >  drivers/clk/clk-vt8500.c | 81
> > +++++++++++++++++++++++------------------------- 1 file changed, 39
> > insertions(+), 42 deletions(-)
> > 
> 
> Hi Stephen,
> 
> Do we need this change during this merge window?
> 

The warning has been there for since before this merge window, so
if anything this is v4.8 material.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project