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Date: Fri, 25 Nov 2016 07:35:46 +0100
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: megous@megous.com
Cc: dev@linux-sunxi.org, Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>, Chen-Yu Tsai <wens@csie.org>,
	Jorik Jonker <jorik@kippendief.biz>,
	"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
	"moderated list:ARM/Allwinner sunXi SoC support" <linux-arm-kernel@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] clk: sunxi-ng: fix PLL_CPUX adjusting on H3
Message-ID: <20161125063546.n3s3dpxdi6ashjtq@lukather>
References: <20161125002852.18097-1-megous@megous.com>
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In-Reply-To: <20161125002852.18097-1-megous@megous.com>
List-ID: <linux-clk.vger.kernel.org>


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On Fri, Nov 25, 2016 at 01:28:47AM +0100, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>=20
> When adjusting PLL_CPUX on H3, the PLL is temporarily driven
> too high, and the system becomes unstable (oopses or hangs).
>=20
> Add a notifier to avoid this situation by temporarily switching
> to a known stable 24 MHz oscillator.
>=20
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Tested-by: Lutz Sammer <johns98@gmx.net>

Applied, thanks!
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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