From: Stephen Boyd <sboyd@codeaurora.org>
To: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org
Subject: Re: [PATCH] clk: cdce925: Fix limit check
Date: Thu, 8 Dec 2016 15:14:44 -0800 [thread overview]
Message-ID: <20161208231444.GX5423@codeaurora.org> (raw)
In-Reply-To: <20161111214905.29481-1-christophe.jaillet@wanadoo.fr>
On 11/11, Christophe JAILLET wrote:
> It is likely that instead of '1>64', 'q>64' was expected.
>
> Moreover, according to datasheet,
> http://www.ti.com/lit/ds/symlink/cdce925.pdf
> SCAS847I - JULY 2007 - REVISED OCTOBER 2016
> PLL settings limits are: 16 <= q <= 63
> So change the upper limit check from 64 to 63.
>
> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2016-12-08 23:14 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-11 21:49 [PATCH] clk: cdce925: Fix limit check Christophe JAILLET
2016-12-08 23:14 ` Stephen Boyd [this message]
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