From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Wed, 5 Apr 2017 14:50:46 -0700 From: Stephen Boyd To: Jonathan Cameron Cc: Rick Altherr , openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org, William Breathitt Gray , Michael Turquette , Andreas Klinger , Rob Herring , Peter Meerwald-Stadler , Quentin Schulz , linux-iio@vger.kernel.org, Zhiyong Tao , Geert Uytterhoeven , Lars-Peter Clausen , Raveendra Padasalagi , Scott Branden , Crestez Dan Leonard , Akinobu Mita , Fabrice Gasnier , Hartmut Knaack , linux-clk@vger.kernel.org Subject: Re: [PATCH v5 2/2] iio: Aspeed ADC Message-ID: <20170405215046.GE7065@codeaurora.org> References: <20170328215259.31622-1-raltherr@google.com> <20170328215259.31622-2-raltherr@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-ID: On 04/01, Jonathan Cameron wrote: > On 28/03/17 22:52, Rick Altherr wrote: > > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold > > interrupts are supported by the hardware but are not currently implemented. > > > > Signed-off-by: Rick Altherr > Two really trivial things inline. I'll fix them whilst applying rather than > having you do a v6 - please do sanity check I haven't messed it up though! > > Applied to the togreg branch of iio.git and pushed out as testing for > the autobuilders to play with it. > Oh I was too late. Blame work. Anyway, I made some comments on v4. If they're fixed in a later patch or discussed on list that's fine. No worries on my end. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project