From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Wed, 19 Apr 2017 09:09:43 -0700 From: Stephen Boyd To: Alexey Firago Cc: mturquette@baylibre.com, robh+dt@kernel.org, marek.vasut@gmail.com, geert@linux-m68k.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 2/3] clk: vc5: Add bindings for IDT VersaClock 5P49V5935 Message-ID: <20170419160943.GW7065@codeaurora.org> References: <1491556344-9465-1-git-send-email-alexey_firago@mentor.com> <1491556344-9465-3-git-send-email-alexey_firago@mentor.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <1491556344-9465-3-git-send-email-alexey_firago@mentor.com> List-ID: On 04/07, Alexey Firago wrote: > IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers. > Input clock source can be taken from either integrated crystal or from > external reference clock. > > Signed-off-by: Alexey Firago > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project