From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.free-electrons.com ([62.4.15.54]:59512 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S968460AbdEXITl (ORCPT ); Wed, 24 May 2017 04:19:41 -0400 Date: Wed, 24 May 2017 10:19:28 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [linux-sunxi] Re: [RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Message-ID: <20170524081928.xcbepxdt7txnadki@flea.home> References: <20170517164354.16399-1-icenowy@aosc.io> <20170517164354.16399-11-icenowy@aosc.io> <20170519180616.vzrlu2avuucsjkiu@flea.home> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="gn2k2r4rgqlpirho" In-Reply-To: Sender: linux-clk-owner@vger.kernel.org List-ID: --gn2k2r4rgqlpirho Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, May 20, 2017 at 02:10:35AM +0800, Icenowy Zheng wrote: >=20 >=20 > =E4=BA=8E 2017=E5=B9=B45=E6=9C=8820=E6=97=A5 GMT+08:00 =E4=B8=8A=E5=8D=88= 2:06:16, Maxime Ripard =E5=86=99=E5=88= =B0: > >On Thu, May 18, 2017 at 12:43:53AM +0800, Icenowy Zheng wrote: > >> As we have already the support for the TV encoder on Allwinner H3, > >add > >> the display engine pipeline device tree nodes to its DTSI file. > >>=20 > >> The H5 pipeline has some differences and will be enabled later. > >>=20 > >> The currently-unused mixer0 and tcon0 are also needed, for the > >> completement of the pipeline. > >>=20 > >> Signed-off-by: Icenowy Zheng > >> --- > >> arch/arm/boot/dts/sun8i-h3.dtsi | 189 > >++++++++++++++++++++++++++++++++++++++++ > >> 1 file changed, 189 insertions(+) > >>=20 > >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > >b/arch/arm/boot/dts/sun8i-h3.dtsi > >> index b36f9f423c39..20172ef92415 100644 > >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >> @@ -41,6 +41,8 @@ > >> */ > >> =20 > >> #include "sunxi-h3-h5.dtsi" > >> +#include > >> +#include > >> =20 > >> / { > >> cpus { > >> @@ -72,6 +74,193 @@ > >> }; > >> }; > >> =20 > >> + de: display-engine { > >> + compatible =3D "allwinner,sun8i-h3-display-engine"; > >> + allwinner,pipelines =3D <&mixer0>, > >> + <&mixer1>; > >> + status =3D "disabled"; > >> + }; > >> + > >> + soc { > >> + display_clocks: clock@1000000 { > >> + compatible =3D "allwinner,sun8i-a83t-de2-clk"; > >> + reg =3D <0x01000000 0x100000>; > >> + clocks =3D <&ccu CLK_BUS_DE>, > >> + <&ccu CLK_DE>; > >> + clock-names =3D "bus", > >> + "mod"; > >> + resets =3D <&ccu RST_BUS_DE>; > >> + #clock-cells =3D <1>; > >> + #reset-cells =3D <1>; > >> + assigned-clocks =3D <&ccu CLK_DE>; > >> + assigned-clock-parents =3D <&ccu CLK_PLL_DE>; > >> + assigned-clock-rates =3D <432000000>; > > > >This shouldn't be set in the DT, but evaluated at runtime when calling > >clk_set_rate. >=20 > Nope, DE2 clock doesn't need evalution, as the clock is decoupled with > DE2 mixers' output signal. (Although it seems that SoCs with larger > plane size will use higher clock.) So it's the display engine that needs that clock to operate properly? This is the wrong DT node to set that value then. It should be in the mixer node, or even better in the mixers' driver. > And setting it to 432MHz is also needed for properly 216MHz clock to > TVE. Just like the parenthood, this can and should be evaluated at runtime. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --gn2k2r4rgqlpirho Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJZJUIQAAoJEBx+YmzsjxAgVxcP/iTUzfmy3TIryWWV0qe9yyY9 gJGYSrF7nzJZ4GHEb5Rq7n+M8kVBjD8UTjLo/p7lXnol6xm/dgMPNzIQ8PWrpEqj dGmSX5qD0wqK+FeWsfBeU9pmsHgOmNkgi9LIaa1uh++M/LPdrHcWaiZBireQCX8L t3Imq+zMgxUWYM4fFnzcZVoMKfOVYI5u8/yisoGOcLnfvltuwT3AuhWvDa4NCRWO l1MHy2S4BuywiNf1C837c7i5KF4xqK5wr6zkPM/2ML9Eqq0KUcnY/2YezyuSREFR DfV+DVmMKPJewVg2AdWfS1DZCMspdF9MAu4lSrA+hCumSck2ltyJ40KuOIrLZRPW Jswz0APX45ZXryV35FliUsCOofkC4r2Lq+kRsfiGw2DF6p5ghvJMofVpgOcfWswK +Dycm6CQZknSsmHki48HNtsY7kk593IbHA4CKM4BPtNJY8qyaKq2lQgauE9jo9Dw 7OVf3uYKvbrnwDWgxbI2A2sRNWxPq1NOTnexGUhwhU7nl4SiOx8i6dXJogaTESK7 +McdnSdKVbTQebYrWArZfHTaMGdfhkxAjqFYUqgZv3Q+vSMN3C4O2IbquTF6KkgH r3uYho8wANY7eMmoBpm2zidUw7u130gf5YINLcxckvT2TXDcj5ekCb28tq8ZCEBd sRI8RqAxXTgE19O2nEya =aMy1 -----END PGP SIGNATURE----- --gn2k2r4rgqlpirho--