Re: [PATCH] clk: mxs: ensure that i.MX28's ref_io clks are not operated too fast

["Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>]

Hello,

On Wed, May 03, 2017 at 04:53:09PM -0300, Fabio Estevam wrote:
> On Wed, May 3, 2017 at 3:56 PM, Uwe Kleine-König
> <u.kleine-koenig@pengutronix.de> wrote:
> > Since commits 7d81397cd93d ("clk: mxs: add clock support for imx28") and
> > 64e2bc413047 ("clk: mxs: imx28: decrease the frequency of ref_io1 for
> > SSP2 and SSP3") the frequencies for ref_io0 and ref_io1 are initialized
> > to 288 MHz because the initial frequency "seems too high to be ssp clock
> > source directly". However this isn't enough to ensure that the frequency
> > isn't increased later again. In fact this happens on my machine as the
> > mxs-spi driver calls clk_set_rate(ssp->clk, 160000000) with ssp being
> > ssp2 which is resolved to
> >
> >         ref_io1.rate = 320 MHz
> >         ssp2_sel.parent = ref_io1
> >         ssp2_div.divider = 2
> >
> > . The observed effect is that reading MISO reliably fails: Instead of
> > the least significant bit the second least significant bit is reported
> > twice. This is probably related to the reports
> >
> >         https://community.nxp.com/thread/290209
> >         https://community.nxp.com/thread/310434
> 
> Adding Stefan on Cc in he could help testing this patch, as he was the
> one that created this thread.

Even though my patch doesn't help Stefan, I think it should be applied
nevertheless as it makes my machine work, just completes the
workaround/fix that is already in mainline and nobody who still has the
issue has the time to debug this further.

Best regards
Uwe

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