From: Stephen Boyd <sboyd@codeaurora.org>
To: Fabio Estevam <festevam@gmail.com>
Cc: shawnguo@kernel.org, kernel@pengutronix.de,
linux-clk@vger.kernel.org, stefan@agner.ch,
Fabio Estevam <fabio.estevam@nxp.com>
Subject: Re: [PATCH v2] clk: imx7d: Fix the powerdown bit location of PLL DDR
Date: Thu, 1 Jun 2017 00:25:45 -0700 [thread overview]
Message-ID: <20170601072545.GS20170@codeaurora.org> (raw)
In-Reply-To: <1494849305-1405-1-git-send-email-festevam@gmail.com>
On 05/15, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> According to the MX7D Reference Manual the powerdown bit of
> CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> Reviewed-by: Stefan Agner <stefan@agner.ch>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-06-01 7:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-15 11:55 [PATCH v2] clk: imx7d: Fix the powerdown bit location of PLL DDR Fabio Estevam
2017-05-23 15:34 ` Fabio Estevam
2017-06-01 7:25 ` Stephen Boyd [this message]
2017-06-06 15:32 ` Leonard Crestez
2017-06-06 15:46 ` Fabio Estevam
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