From: Stephen Boyd <sboyd@codeaurora.org>
To: Fabio Estevam <fabio.estevam@nxp.com>
Cc: shawnguo@kernel.org, kernel@pengutronix.de, stefan@agner.ch,
linux-clk@vger.kernel.org, leonard.crestez@nxp.com,
festevam@gmail.com
Subject: Re: [PATCH] clk: imx7d: Fix the DDR PLL enable bit
Date: Tue, 6 Jun 2017 17:42:49 -0700 [thread overview]
Message-ID: <20170607004249.GM20170@codeaurora.org> (raw)
In-Reply-To: <1496763954-10981-1-git-send-email-fabio.estevam@nxp.com>
On 06/06, Fabio Estevam wrote:
> Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location
> of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.
>
> Fix it accordingly to avoid a kernel hang.
>
> Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2017-06-07 0:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-06 15:45 [PATCH] clk: imx7d: Fix the DDR PLL enable bit Fabio Estevam
2017-06-06 16:29 ` Stefan Agner
2017-06-07 0:42 ` Stephen Boyd [this message]
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