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From: Marek Vasut <marek.vasut@gmail.com>
To: linux-clk@vger.kernel.org
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Alexey Firago <alexey_firago@mentor.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	linux-renesas-soc@vger.kernel.org
Subject: [PATCH 2/8] clk: vc5: Fix trivial typo
Date: Thu, 29 Jun 2017 12:18:45 +0200	[thread overview]
Message-ID: <20170629101851.23972-2-marek.vasut@gmail.com> (raw)
In-Reply-To: <20170629101851.23972-1-marek.vasut@gmail.com>

From: Marek Vasut <marek.vasut+renesas@gmail.com>

Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
---
 drivers/clk/clk-versaclock5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 60bf4afb51bd..d835d48cf14d 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -520,7 +520,7 @@ static void vc5_clk_out_unprepare(struct clk_hw *hw)
 	struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 	struct vc5_driver_data *vc5 = hwdata->vc5;
 
-	/* Enable the clock buffer */
+	/* Disable the clock buffer */
 	regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
 			   VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
 }
-- 
2.11.0

  reply	other threads:[~2017-06-29 10:18 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-29 10:18 [PATCH 1/8] clk: vc5: Prevent division by zero on unconfigured outputs Marek Vasut
2017-06-29 10:18 ` Marek Vasut [this message]
2017-06-29 10:18 ` [PATCH 3/8] clk: vc5: Do not warn about disabled output buffer input muxes Marek Vasut
2017-06-30 19:26   ` Stephen Boyd
2017-07-01 20:00     ` Marek Vasut
2017-06-29 10:18 ` [PATCH 4/8] clk: vc5: Configure the output buffer input mux on prepare Marek Vasut
2017-06-29 10:18 ` [PATCH 5/8] clk: vc5: Split clock input mux and predivider Marek Vasut
2017-06-29 10:18 ` [PATCH 6/8] clk: vc5: Add support for the input frequency doubler Marek Vasut
2017-06-29 10:18 ` [PATCH 7/8] clk: vc5: Add bindings for IDT VersaClock 5P49V6901 Marek Vasut
2017-06-29 11:38   ` Geert Uytterhoeven
2017-06-29 15:49     ` Marek Vasut
2017-06-29 16:27       ` Geert Uytterhoeven
2017-06-29 10:18 ` [PATCH 8/8] clk: vc5: Add support " Marek Vasut
2017-06-29 11:41   ` Geert Uytterhoeven
2017-06-29 15:54     ` Marek Vasut
2017-06-29 10:26 ` [PATCH 1/8] clk: vc5: Prevent division by zero on unconfigured outputs Laurent Pinchart
  -- strict thread matches above, loose matches on Subject: below --
2017-07-01 20:04 Marek Vasut
2017-07-01 20:04 ` [PATCH 2/8] clk: vc5: Fix trivial typo Marek Vasut
2017-07-02  8:20   ` Laurent Pinchart

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