Re: [PATCH] clk: tegra30: fix cclk_lp divisor register

[Peter De Schrijver <pdeschrijver@nvidia.com>]

On Tue, Sep 19, 2017 at 04:48:10AM +0200, Micha=C5=82 Miros=C5=82aw wrote:
> According to comments in code and common sense, cclk_lp uses its
> own divisor, not cclk_g's.
>=20

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

Note that we model multiple clocks which touch the same hw register which
will likely not work if you would use more than one of them. So probably
this needs to be refactored somehow. The clock topology is rather odd
though as the divider only applies to certain inputs for cclk_lp.

> Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
> Signed-off-by: Micha=C5=82 Miros=C5=82aw <mirq-linux@rere.qmqm.pl>
> ---
>  drivers/clk/tegra/clk-tegra30.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegr=
a30.c
> index 8f5a3e7c3bf9..95b7df4a8abd 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -964,7 +964,7 @@ static void __init tegra30_super_clk_init(void)
>  	 * U71 divider of cclk_lp.
>  	 */
>  	clk =3D tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
> -				clk_base + SUPER_CCLKG_DIVIDER, 0,
> +				clk_base + SUPER_CCLKLP_DIVIDER, 0,
>  				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
>  	clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
> =20
> --=20
> 2.11.0
>=20
> --
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