* [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle [not found] <CGME20170919100345eucas1p1391a495dab09faecdc2acf9635e4c42d@eucas1p1.samsung.com> @ 2017-09-19 10:01 ` Marek Szyprowski 2017-09-19 10:28 ` Sylwester Nawrocki 2017-10-04 16:19 ` Stephen Boyd 0 siblings, 2 replies; 5+ messages in thread From: Marek Szyprowski @ 2017-09-19 10:01 UTC (permalink / raw) To: linux-clk, linux-samsung-soc Cc: Marek Szyprowski, Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz, Michael Turquette, Stephen Boyd, stable Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that VPLL and EPPL clocks were always enabled because the enable bit was never touched. Those clocks have to be enabled during suspend/resume cycle, because otherwise board fails to enter sleep mode. This patch enables them unconditionally before entering system suspend state. System restore function will set them to the previous state saved in the register cache done before that unconditional enable. Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") CC: stable@vger.kernel.org # v4.13 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> --- drivers/clk/samsung/clk-exynos4.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..d8d3cb67b402 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -294,6 +294,18 @@ enum exynos4_plls { #define PLL_ENABLED (1 << 31) #define PLL_LOCKED (1 << 29) +static void exynos4_clk_enable_pll(u32 reg) +{ + u32 pll_con = readl(reg_base + reg); + pll_con |= PLL_ENABLED; + writel(pll_con, reg_base + reg); + + while (!(pll_con & PLL_LOCKED)) { + cpu_relax(); + pll_con = readl(reg_base + reg); + } +} + static void exynos4_clk_wait_for_pll(u32 reg) { u32 pll_con; @@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) samsung_clk_save(reg_base, exynos4_save_pll, ARRAY_SIZE(exynos4_clk_pll_regs)); + exynos4_clk_enable_pll(EPLL_CON0); + exynos4_clk_enable_pll(VPLL_CON0); + if (exynos4_soc == EXYNOS4210) { samsung_clk_save(reg_base, exynos4_save_soc, ARRAY_SIZE(exynos4210_clk_save)); -- 1.9.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle 2017-09-19 10:01 ` [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Marek Szyprowski @ 2017-09-19 10:28 ` Sylwester Nawrocki 2017-10-04 6:08 ` Marek Szyprowski 2017-10-04 16:19 ` Stephen Boyd 1 sibling, 1 reply; 5+ messages in thread From: Sylwester Nawrocki @ 2017-09-19 10:28 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd Cc: Marek Szyprowski, linux-clk, linux-samsung-soc, Chanwoo Choi, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz, stable On 09/19/2017 12:01 PM, Marek Szyprowski wrote: > Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for > PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that > VPLL and EPPL clocks were always enabled because the enable bit was never > touched. Those clocks have to be enabled during suspend/resume cycle, > because otherwise board fails to enter sleep mode. This patch enables them > unconditionally before entering system suspend state. System restore > function will set them to the previous state saved in the register cache > done before that unconditional enable. > > Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") > CC: stable@vger.kernel.org # v4.13 > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Stephen, Mike, could you please apply this patch directly? Thanks, Sylwester > --- > drivers/clk/samsung/clk-exynos4.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c > index e40b77583c47..d8d3cb67b402 100644 > --- a/drivers/clk/samsung/clk-exynos4.c > +++ b/drivers/clk/samsung/clk-exynos4.c > @@ -294,6 +294,18 @@ enum exynos4_plls { > #define PLL_ENABLED (1 << 31) > #define PLL_LOCKED (1 << 29) > > +static void exynos4_clk_enable_pll(u32 reg) > +{ > + u32 pll_con = readl(reg_base + reg); > + pll_con |= PLL_ENABLED; > + writel(pll_con, reg_base + reg); > + > + while (!(pll_con & PLL_LOCKED)) { > + cpu_relax(); > + pll_con = readl(reg_base + reg); > + } > +} > + > static void exynos4_clk_wait_for_pll(u32 reg) > { > u32 pll_con; > @@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) > samsung_clk_save(reg_base, exynos4_save_pll, > ARRAY_SIZE(exynos4_clk_pll_regs)); > > + exynos4_clk_enable_pll(EPLL_CON0); > + exynos4_clk_enable_pll(VPLL_CON0); > + > if (exynos4_soc == EXYNOS4210) { > samsung_clk_save(reg_base, exynos4_save_soc, > ARRAY_SIZE(exynos4210_clk_save)); ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle 2017-09-19 10:28 ` Sylwester Nawrocki @ 2017-10-04 6:08 ` Marek Szyprowski 2017-10-04 16:18 ` Stephen Boyd 0 siblings, 1 reply; 5+ messages in thread From: Marek Szyprowski @ 2017-10-04 6:08 UTC (permalink / raw) To: Sylwester Nawrocki, Michael Turquette, Stephen Boyd Cc: linux-clk, linux-samsung-soc, Chanwoo Choi, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz, stable Hi All, On 2017-09-19 12:28, Sylwester Nawrocki wrote: > On 09/19/2017 12:01 PM, Marek Szyprowski wrote: >> Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for >> PLL36XX clocks") added enable/disable operations to PLL clocks. Prior >> that >> VPLL and EPPL clocks were always enabled because the enable bit was >> never >> touched. Those clocks have to be enabled during suspend/resume cycle, >> because otherwise board fails to enter sleep mode. This patch enables >> them >> unconditionally before entering system suspend state. System restore >> function will set them to the previous state saved in the register cache >> done before that unconditional enable. >> >> Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for >> PLL36XX clocks") >> CC: stable@vger.kernel.org # v4.13 >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> >> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> >> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > > Stephen, Mike, could you please apply this patch directly? Gentle ping. Any chance to have this patch merged as a fix to v4.14-rcX? > ... Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle 2017-10-04 6:08 ` Marek Szyprowski @ 2017-10-04 16:18 ` Stephen Boyd 0 siblings, 0 replies; 5+ messages in thread From: Stephen Boyd @ 2017-10-04 16:18 UTC (permalink / raw) To: Marek Szyprowski Cc: Sylwester Nawrocki, Michael Turquette, linux-clk, linux-samsung-soc, Chanwoo Choi, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz, stable On 10/04, Marek Szyprowski wrote: > Hi All, > > On 2017-09-19 12:28, Sylwester Nawrocki wrote: > >On 09/19/2017 12:01 PM, Marek Szyprowski wrote: > >>Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for > >>PLL36XX clocks") added enable/disable operations to PLL clocks. > >>Prior that > >>VPLL and EPPL clocks were always enabled because the enable bit > >>was never > >>touched. Those clocks have to be enabled during suspend/resume cycle, > >>because otherwise board fails to enter sleep mode. This patch > >>enables them > >>unconditionally before entering system suspend state. System restore > >>function will set them to the previous state saved in the register cache > >>done before that unconditional enable. > >> > >>Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation > >>for PLL36XX clocks") > >>CC: stable@vger.kernel.org # v4.13 > >>Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > >>Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> > >>Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > >>Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > > > >Stephen, Mike, could you please apply this patch directly? > > Gentle ping. > > Any chance to have this patch merged as a fix to v4.14-rcX? > Sure. I thought this was an old regression for pre-v4.14 rcs though. Sounds like it's causing more pain though, so I'll pick it into fixes. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle 2017-09-19 10:01 ` [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Marek Szyprowski 2017-09-19 10:28 ` Sylwester Nawrocki @ 2017-10-04 16:19 ` Stephen Boyd 1 sibling, 0 replies; 5+ messages in thread From: Stephen Boyd @ 2017-10-04 16:19 UTC (permalink / raw) To: Marek Szyprowski Cc: linux-clk, linux-samsung-soc, Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz, Michael Turquette, stable On 09/19, Marek Szyprowski wrote: > Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for > PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that > VPLL and EPPL clocks were always enabled because the enable bit was never > touched. Those clocks have to be enabled during suspend/resume cycle, > because otherwise board fails to enter sleep mode. This patch enables them > unconditionally before entering system suspend state. System restore > function will set them to the previous state saved in the register cache > done before that unconditional enable. > > Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") > CC: stable@vger.kernel.org # v4.13 > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > --- Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <CGME20170919100345eucas1p1391a495dab09faecdc2acf9635e4c42d@eucas1p1.samsung.com>
2017-09-19 10:01 ` [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Marek Szyprowski
2017-09-19 10:28 ` Sylwester Nawrocki
2017-10-04 6:08 ` Marek Szyprowski
2017-10-04 16:18 ` Stephen Boyd
2017-10-04 16:19 ` Stephen Boyd
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