From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Wed, 4 Oct 2017 09:19:25 -0700 From: Stephen Boyd To: Marek Szyprowski Cc: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Michael Turquette , stable@vger.kernel.org Subject: Re: [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Message-ID: <20171004161925.GW457@codeaurora.org> References: <1505815279-19097-1-git-send-email-m.szyprowski@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <1505815279-19097-1-git-send-email-m.szyprowski@samsung.com> List-ID: On 09/19, Marek Szyprowski wrote: > Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for > PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that > VPLL and EPPL clocks were always enabled because the enable bit was never > touched. Those clocks have to be enabled during suspend/resume cycle, > because otherwise board fails to enter sleep mode. This patch enables them > unconditionally before entering system suspend state. System restore > function will set them to the previous state saved in the register cache > done before that unconditional enable. > > Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") > CC: stable@vger.kernel.org # v4.13 > Signed-off-by: Marek Szyprowski > Reviewed-by: Chanwoo Choi > Reviewed-by: Krzysztof Kozlowski > Acked-by: Sylwester Nawrocki > --- Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project