From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Thu, 2 Nov 2017 01:12:05 -0700 From: Stephen Boyd To: sean.wang@mediatek.com Cc: mturquette@baylibre.com, robh+dt@kernel.org, matthias.bgg@gmail.com, mark.rutland@arm.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen Zhong Subject: Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock Message-ID: <20171102081205.GG11011@codeaurora.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-ID: On 10/05, sean.wang@mediatek.com wrote: > From: Chen Zhong > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > > Signed-off-by: Chen Zhong > Signed-off-by: Sean Wang > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project