From: Stephen Boyd <sboyd@codeaurora.org>
To: "Michał Mirosław" <mirq-linux@rere.qmqm.pl>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH] clk: tegra30: fix cclk_lp divisor register
Date: Thu, 2 Nov 2017 01:17:10 -0700 [thread overview]
Message-ID: <20171102081710.GN11011@codeaurora.org> (raw)
In-Reply-To: <f54b8ff896d3dcbae51741b817d65a7e9a21987a.1505789180.git.mirq-linux@rere.qmqm.pl>
On 09/19, Michał Mirosław wrote:
> According to comments in code and common sense, cclk_lp uses its
> own divisor, not cclk_g's.
>
> Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2017-11-02 8:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <f54b8ff896d3dcbae51741b817d65a7e9a21987a.1505789180.git.mirq-linux@rere.qmqm.pl>
2017-09-19 8:54 ` [PATCH] clk: tegra30: fix cclk_lp divisor register Peter De Schrijver
2017-11-02 8:17 ` Stephen Boyd [this message]
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