From: Stephen Boyd <sboyd@codeaurora.org>
To: Sergej Sawazki <sergej@taudac.com>
Cc: mturquette@baylibre.com, sebastian.hesselbarth@gmail.com,
linux@armlinux.org.uk, linux-clk@vger.kernel.org, ce3a@gmx.de,
Rabeeh Khoury <rabeeh@solid-run.com>
Subject: Re: [PATCH v2 1/2] clk: si5351: Add DT property to enable PLL reset
Date: Thu, 21 Dec 2017 18:11:13 -0800 [thread overview]
Message-ID: <20171222021113.GM7997@codeaurora.org> (raw)
In-Reply-To: <1505562282-9111-2-git-send-email-sergej@taudac.com>
On 09/16, Sergej Sawazki wrote:
> Add optional output clock DT property to enable PLL reset when a clock
> output is enabled.
>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Signed-off-by: Sergej Sawazki <sergej@taudac.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-12-22 2:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-16 11:44 [PATCH v2 0/2] clk: si5351: PLL reset fixes Sergej Sawazki
2017-09-16 11:44 ` [PATCH v2 1/2] clk: si5351: Add DT property to enable PLL reset Sergej Sawazki
2017-12-22 2:11 ` Stephen Boyd [this message]
2017-09-16 11:44 ` [PATCH v2 2/2] clk: si5351: Apply PLL soft reset before enabling the outputs Sergej Sawazki
2017-12-22 2:11 ` Stephen Boyd
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